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1. 发明专利

JPH04196340A DIELECTRICS ISOLATION SUBSTRATE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04196340A
公开(公告)日：1992-07-16
申请号：JP32633690
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SUZUKI ITARU , SAKANIWA HIROTAKA , INOUE HIRONORI , URUNO TOSHIO , KURITA SHINICHI
IPC分类号： H01L21/762 , H01L21/02 , H01L21/76 , H01L27/12
摘要： PURPOSE:To eliminate the occurrence of outer peripheral polishing sag thereby avoiding the stain and separation of a wafer in the later steps by covering the peripheral part of an isolation substrate with a single crystal semiconductor. CONSTITUTION:The peripheral parts of an isolation substrate 5 are scraped off to reduce the diameter of the substrate and after bonding the substrate 5 onto the single crystal Si substrate 6 to be a supporting body, both substrate 5, 6 are joined to each other using produced silicon oxide by thermal oxidation step in oxidizing atmosphere to form a joined substrate 71. At this time, in order to bond together both substrates 5, 6, the occurrence of non-bonded part on the periphery of the contact surface 51 can be avoided by making the diameter of single crystal Si substrate 6 larger than that of the standard diameter so as to stick the isolation substrate 5 to the single crystal Si substrate 6 not through the intermediary of a bonding layer thereby making no gaps at the outer-most end of the bonding substrate 51. Through these procedures, the polishing sag can be perfectly removed thereby avoiding the separation from the wafer bonding surface 51 due to local etching step.

2. 发明专利

JPH0867995A PLASMA ETCHING DEVICE 失效
公开(公告)号：JPH0867995A
公开(公告)日：1996-03-12
申请号：JP20329994
申请日：1994-08-29
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： TAKAHASHI KAZUYUKI , HAYASHI SHOJI , SHINNO YUJI , SAKANIWA HIROTAKA
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065
摘要： PURPOSE: To increase the number of produced nondefective semiconductor devices and to improve reliability by uniformizing the etching rate in the etching surface of a material to be etched. CONSTITUTION: A material 12 to be etched is placed on a lower electrode (stage) 11, a chamber 1 is evacuated from an exhaust port 5 to a specified vacuum, and a reacting gas variable with the kind of the material 12 is introduced from an inlet 6. A high-frequency electric field is impressed on an upper electrode 10, the upper electrode 10 or the lower electrode is rotated at a specified speed, and the material 12 is etched in a plasma state.

3. 发明专利

JPH08222625A MANUFACTURE OF DIELECTRIC ISOLATION BOARD 失效
公开(公告)号：JPH08222625A
公开(公告)日：1996-08-30
申请号：JP2148495
申请日：1995-02-09
申请人： HITACHI LTD
发明人： SAKURABA KOJI , HAYASHI SHOJI , SHINNO YUJI , SAKANIWA HIROTAKA
IPC分类号： H01L21/762 , H01L21/02 , H01L27/12
摘要： PURPOSE: To eliminate a bent of a substrate at the time of heat treating at a high temperature by forming an insulating film on a single crystalline silicon substrate having grooves, then removing the film of the part which is not used as an integrated circuit, and simultaneously depositing a single crystalline silicon layer together with a polycrystalline silicon layer on the other part. CONSTITUTION: Insulating films 3, 4 are formed on a single crystalline silicon substrate 1 having grooves 2 on one main surface, and a polycrystalline silicon 6 is deposited on the main surface having the grooves 2 by a vapor growing method. Then, the surface of the silicon layer 6 is ground and polished to be flattened mirror surface, and a dielectric isolation substrate 13 is manufactured via the step of laminating the mirror surface and the main surface of a single crystalline silicon substrate 10. In this case, the film 3 of the part 5 which is not used as an integrated circuit on the main surface having the grooves 3 is removed, and a single crystalline silicon 7 is deposited at the part simultaneously by a vapor growing method to prevent the vent of the substrate 13. For example, the insulating film removed part of the part 5 which is not used as the integrated circuit is arranged on the entirety of the substrate.

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