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1. 发明专利

IN166534B APPARATUS FOR SWITCHING MULTI-RUNNING CENTRAL PROCESSING UNITS 未知
公开(公告)号：IN166534B
公开(公告)日：1990-05-26
申请号：IN41CA1987
申请日：1987-01-13
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： YAMAOKA HIROMASA , WAKITA AKIHIRO , SAITOW JUNJU , TENNICHI YASUHIRO , SHIMOYAMA KAZUHIKO , SASAKI WATARU , KAJIYAMA YOSHINORI
IPC分类号： G06F13/00

2. 发明专利

IN165881B APPARATUS FOR ACHIEVING MASTERLESS SERIES BUS OCCUPATION CONTROL 未知
公开(公告)号：IN165881B
公开(公告)日：1990-02-03
申请号：IN5CA1987
申请日：1987-01-01
申请人： HITACHI ENG CO LTD , HITACHI LTD
发明人： YAMAOKA HIROMASA , WAKITA AKIHIRO , SAITO JUNJU , TENNICHI YASUHIRO , SHIMOYAMA KAZUHIKO
IPC分类号： G06F13/38 , G06F7/00 , G06F13/20 , G06F13/372 , G06F15/16

3. 发明专利

JPH05307491A 失效
公开(公告)号：JPH05307491A
公开(公告)日：1993-11-19
申请号：JP486387
申请日：1987-01-14
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： YAMAOKA HIROMASA , SHIMOYAMA KAZUHIKO , AMAHI YASUHIRO , SAITOU SUMIHISA , SASAKI WATARU , WAKITA AKIHIRO , KAWADA SHINICHI
IPC分类号： G06F11/20 , G06F15/16
摘要： PURPOSE:To attain compact duplexing by incorporating a CPU with a means which judges the state of the CPU of the other party and decides that it becomes an ordinary working system. CONSTITUTION:The CPU consists of the CPU-A1 and the CPU-B1, and they are connected respectively to a transmission line 50 and a system bus 60, and usually, the CPU-A1 is the ordinary working system, and inputs data from an input/output device (I/O) 3, and executes arithmetic operation in a micro- processing unit(MPU) 4, and instructs the I/O 3 and outputs the data to the same. The CPU-B1 of a standby system is inhibited from accessing the I/O 3 since an SYSBEN signal 113 is turned OFF, and receives the data from the CPU-A1 through the transmission line 50, and executes the same arithmetic operation as the CPU-A1, and stands by. When the CPU-A1 stops, an ordinary working/standby judgement circuit 5 detects that the CPU-B1 is turned to the ordinary working system by the turning-OFF of an SYSRUN signal 101, and turns ON the SYSBEN signal 113, and the CPU-B1 starts write-in to the I/O 3.

4. 发明专利

JPH03125251A DATA MULTI-PROCESSING SYSTEM AND ITS BUS SELECTION METHOD 失效
公开(公告)号：JPH03125251A
公开(公告)日：1991-05-28
申请号：JP26362689
申请日：1989-10-09
申请人： HITACHI LTD , HITACHI ENG CO LTD , HITACHI PROCESS COMPUTER ENG
发明人： IGARI KUNIYUKI , YAMAOKA HIROMASA , TAKAKURA MITSUO , NOGUCHI HIROYUKI , YOKOTA TAKAHIRO , KOBAYASHI MASAMITSU
IPC分类号： G06F15/16 , G06F13/362 , G06F15/177
摘要： PURPOSE:To ensure a smooth access to one of two units from the other one by using a main bus arbiter to control the access carried out in a main unit and the access given from a subunit and granting the use of a bus only to a specific processor based on the prescribed priority. CONSTITUTION:A main bus arbiter 18 is connected to a sub-bus arbiter 30 via a main sub-bus 40 set in parallel to a main bus. A main memory 16 is connected to a submemory 28 via a system bus 38. Then the arbiter 18 grants the use of a main local bus 24 to a specific processor only based on the prescribed priority in response to the bus using request signals received from a main processor 14 and a subprocessor 26 of its own system and another system. Then the arbiter 30 grants the use of a sublocal bus 36 to a specific processor only based on the prescribed priority in response to the bus using request given from the processor 26 of its own. Thus an access is easily given to one of two units from the other one.

5. 发明专利

JPS6015704A MULTIPLEX STRUCTURE CONTROLLER 失效
公开(公告)号：JPS6015704A
公开(公告)日：1985-01-26
申请号：JP12365583
申请日：1983-07-07
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： HAMADA KANMAN , SUGIMOTO NORIHIKO , HIROKI TAKESHI , IWASA YUUZABUROU , YAMAOKA HIROMASA , OKAMOTO TADASHI , INADA KAZUHISA
IPC分类号： G05B9/03
摘要： PURPOSE:To improve the reliability of a multiplex structure controller by identifying the normal or abnormal state of a controller as well as a route reaching an output switch from the controller. CONSTITUTION:The diagnosis parts 141A and 141B of output signal diagnosis boards 14A and 14B collate the supplied control signals CA and CB with each other for every fixed period T0 and then delivers a switch command to deliver the signal CA or CB of a system A or B which is previously decided if the coincidence is obtained from said collation. When no coincidence is obtained between both control signals, each control signal of the preceding collation is compared with the present control signal to select the signal CB, for example, which has a smaller degree of variation. Based on this selection, a switch command is delivered to relay drivers 145- and 146- from a diagnosis part 141-. Thus relays 131-134 and 135-138 are turned off and on respectively at a time point t3. Then the signal CB is delivered. While the discordance signal is sent to controller diagnosis boards 12A and 12B as soon as the discordance is detected from said collation. Thus the question-answer diagnosis is given to controllers 1A and 1B, and at the same time a re-execution command is delivered (t5).

6. 发明专利

JPH0568901B2 失效
公开(公告)号：JPH0568901B2
公开(公告)日：1993-09-29
申请号：JP19943985
申请日：1985-09-11
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： SAITO SUMIHISA , WAKITA AKIHIRO , SHIMOYAMA KAZUHIKO , AMAHI YASUHIRO , YAMAOKA HIROMASA
IPC分类号： H04L12/40

7. 发明专利

JPH01114902A PROCESS CONTROLLER 失效
公开(公告)号：JPH01114902A
公开(公告)日：1989-05-08
申请号：JP27188687
申请日：1987-10-29
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： OHASHI AKIHIRO , YAMAOKA HIROMASA , KURISU YOFUMI , NOZATO YORIHISA , KAMIYAMA KENZO , TAKAKURA MITSUO , NOGUCHI HIROYUKI , SAITOU SUMIHISA
IPC分类号： G05B13/02 , G05B13/00
摘要： PURPOSE:To attain parallel processing of determination for an optimum parameter and a control variable by separating a control object unit, the determination of a model of controlled system, a parameter determining part, and a control variable determining part from each other and setting up a bus for inputting/ outputting the quantity of state of the controlled system to the shortest length. CONSTITUTION:The model of controlled system which may be changed in accordance with an operating condition is corrected and determined by a controlling computer 6 and obtained parameters and gain are transmitted to process control parts 1-1, 1-2 through a network 8. The control parts 1-1, 1-2 calculate control output vectors based on the quantity 27 of state inputted from the controlled system 7 through a process unit device 2 and an optimum gain matrix applied from the computer 6 and output the calculated vectors to the controlled system 7 through a process output device 3. Said processing is executed by a processing unit 21 in the control part 1-1 and a functional process input device 4 calculates an offset value, etc., and outputs the calculated result to the controlled system 7 as a control signal 24.

8. 发明专利

JPS62210547A DIAGNOSING METHOD FOR ERROR DETECTION CIRCUIT 失效
公开(公告)号：JPS62210547A
公开(公告)日：1987-09-16
申请号：JP5250786
申请日：1986-03-12
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： ISAKA YOSHINOBU , FUNAKOSHI SHUJI , YAMAOKA HIROMASA , KURISU YOFUMI , WAKITA AKIHIRO
IPC分类号： G06F11/08 , G06F12/16
摘要： PURPOSE:To generate an error data intentionally, to facilitate the diagnosis of an error detection circuit, and to realize exactness, by writing data independently on a data memory and a redundancy bit memory. CONSTITUTION:Generally, other than an address 101, virtual addresses 103 and 104 having the same address ranges as that of the address 101, and another address areas, are provided. When the address 103 is inputted to a memory selector 1, a data RAM cell 107 is outputted, and when the address 104 is inputted to the selector 1, a parity RAM cell 106 is outputted. In this way, a switching between a normal mode and a diagnostic mode can be performed by using those addresses in a diagnostic mode time, and a RAM can be accessed individually by providing plural virtual addresses.

9. 发明专利

JPS62162159A CONTROL METHOD FOR MASTERLESS SERIAL BUS OCCUPATION 失效
公开(公告)号：JPS62162159A
公开(公告)日：1987-07-18
申请号：JP343486
申请日：1986-01-13
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： YAMAOKA HIROMASA , WAKITA AKIHIRO , SAITOU SUMIHISA , AMAHI YASUHIRO , SHIMOYAMA KAZUHIKO
IPC分类号： G06F13/38 , G06F7/00 , G06F13/20 , G06F13/372 , G06F15/16
摘要： PURPOSE:To attain the control of the occupation of a serial bus free from collision of data on a bus by obtaining an optimum transmission queuing time from a transmission PC number in a transmission data format, a transmission time interval set by a setting device, and the amount of transmission data in the transmission data format to set it in the counting devices of the respective PCs. CONSTITUTION:An MPU 24 reads the self-PC number, the transmission interval, and the total PC number set in the setting device 27, and stores them in a memory 26. Then the MPU 24 sets the maximum queuing time in a counting device 25 and comes to a bus monitoring state in order to confirm that there is another PC on the serial bus currently being transmitted. In case there is no PC to be data-transmitted on the serial bus, the device 25 supplies to the MPU 24 a transmission timing after the lapsing of the maximum queuing time, and the MPU 24 executes the transmission. After ending the transmission, the MPU 24 gets again the maximum queuing time in the device 25, and executes the arithmetic and control operation. The above described operation is repeated thereafter.

10. 发明专利

JPS6260334A METHOD AND EQUIPMENT FOR SWITCHING MULTIPLEX TRANSMISSION LINE 失效
公开(公告)号：JPS6260334A
公开(公告)日：1987-03-17
申请号：JP19943985
申请日：1985-09-11
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： SAITOU SUMIHISA , WAKITA AKIHIRO , SHIMOYAMA KAZUHIKO , AMAHI YASUHIRO , YAMAOKA HIROMASA
IPC分类号： H04L12/40
摘要： PURPOSE:To improve the maintenance maintenance property and reliability by sending simultaneously a data to all multiplex system transmission lines to apply self-diagnosis in case of transmission, disconnecting a transmission line if it is decided that the inside of its own station has an error and receiving the data only from a transmission line decided as normal in case of the reception. CONSTITUTION:A data sent to transmission lines 10, 11 is subjected to normality/ abnormity decision by a deciding circuit 52. Then the result of decision is sent to a transmission line diagnostic circuit 58 to repeat the diagnosis of the transmission line. When the fault is detected, the relay of the corresponding transmission line side is opened to apply self-diagnosis in its own station. As a result, when it is normal, the relay is reconnected and when an error still exists, the relay remains disconnected as it is. The data on the transmission line 10 is received via a reception circuit 52, the normality/abnormity decision of the reception data is applied in the deciding circuit 52, and only when the data is normal as the result of decision, a timer 53 is reset. When normal reception is not executed, the timer 53 is not reset and the changeover command of the reception line is given to a reception line indicator 57.

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