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1. 发明专利

DE602004012226D1 未知
公开(公告)号：DE602004012226D1
公开(公告)日：2008-04-17
申请号：DE602004012226
申请日：2004-12-23
申请人： HITACHI LTD , ELPIDA MEMORY INC
发明人： HANZAWA SATORU , SAKATA TAKESHI , KAJIGAYA KAZUHIKO
IPC分类号： G11C11/401 , G11C15/04 , G11C11/56
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value '1'; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

2. 发明专利

DE102006035815A1 未知
公开(公告)号：DE102006035815A1
公开(公告)日：2007-02-22
申请号：DE102006035815
申请日：2006-08-01
申请人： HITACHI LTD , ELPIDA MEMORY INC
发明人： SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , HANZAWA SATORU , KAJIGAYA KAZUHIKO
IPC分类号： G11C29/52 , G11C29/24
摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

3. 发明专利

DE602004012226T2 未知
公开(公告)号：DE602004012226T2
公开(公告)日：2009-03-12
申请号：DE602004012226
申请日：2004-12-23
申请人： HITACHI LTD , ELPIDA MEMORY INC
发明人： HANZAWA SATORU , SAKATA TAKESHI , KAJIGAYA KAZUHIKO
IPC分类号： G11C11/401 , G11C15/04 , G11C11/56
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value '1'; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

4. 发明公开

EP1688957A4 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译： INTEGRIERTES HALBLEITERSCHALTUNGSBAUEMENT
公开(公告)号：EP1688957A4
公开(公告)日：2007-03-28
申请号：EP03774141
申请日：2003-11-21
申请人： HITACHI LTD , ELPIDA MEMORY INC
发明人： HANZAWA S , SHIGETA J , KIMURA S , SAKATA T , TAKEMURA R , KAJIGAYA KAZUHIKO
IPC分类号： G11C15/04
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array comprising memory cells employing a memory circuit STC and a comparison circuit CP, any one of source and drain electrodes of a transistor having a gate electrode being connected with a search line among a plurality of transistors constituting the comparison circuit CP is connected with a match line HMLr being precharged with a high voltage. A match line decision circuit MDr is arranged in a match line LMLr being precharged with a low voltage and a comparison signal voltage generated in that match line is discriminated depending on the comparison results of information. With such arrangement and operation of a memory array, comparison operation can be carried out at high speed with low power while avoiding the effect of search line driving noise in a pair of match lines. A low power content addressable memory capable of performing search operation at high speed can thereby be realized.
摘要翻译：在包括使用存储器电路STC和比较电路CP的存储器单元的存储器阵列中，连接构成比较电路CP的多个晶体管中的具有与搜索线连接的栅电极的晶体管的源极和漏极中的任一个用匹配线HMLr预充高电压。匹配线决定电路MDr布置在用低电压预充电的匹配线LMLr中，并且根据信息的比较结果来识别在匹配线中产生的比较信号电压。利用存储器阵列的这种布置和操作，可以以低功率高速执行比较操作，同时避免一对匹配线中的搜索线驱动噪声的影响。由此可以实现能够高速执行搜索操作的低功率内容可寻址存储器。

5. 发明专利

DE102008028514A1 未知
公开(公告)号：DE102008028514A1
公开(公告)日：2009-01-08
申请号：DE102008028514
申请日：2008-06-16
申请人： ELPIDA MEMORY INC
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C11/4074
摘要： To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage.

6. 发明专利

DE102008021348A1 未知
公开(公告)号：DE102008021348A1
公开(公告)日：2008-11-27
申请号：DE102008021348
申请日：2008-04-29
申请人： ELPIDA MEMORY INC
发明人： KAJIGAYA KAZUHIKO
IPC分类号： G11C7/22 , G06F13/14 , G06F13/18
摘要： In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data.

7. 发明授权

US6275440B2 Semiconductor integrated circuit device and method of activating the same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US6275440B2
公开(公告)日：2001-08-14
申请号：US72927300
申请日：2000-12-05
申请人： HITACHI LTD
发明人： NODA HIROMASA , AOKI MASAKAZU , IDEI YOUJI , KAJIGAYA KAZUHIKO , NAGASHIMA OSAMU , ITOH KIYOO , HORIGUCHI MASASHI , SAKATA TAKESHI
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , H03K19/00 , G11C7/00
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线的并行设置多个开关MOSFET，其在达到其非电压时不需要存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

8. 发明授权

US6411543B2 Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device 有权
标题翻译：动态随机存取存储器（RAM），半导体存储器件和半导体集成电路（IC）器件
公开(公告)号：US6411543B2
公开(公告)日：2002-06-25
申请号：US75517001
申请日：2001-01-08
申请人： HITACHI LTD , HITACHI ULSI ENG CORP
发明人： NARUI SEIJI , NAGASHIMA OSAMU , HASEGAWA MASATOSHI , FUJISAWA HIROKI , MIYATAKE SHINICHI , SUZUKI TSUYUKI , AOKI YASUNOBU , TAKAHASHI TSUTOM , KAJIGAYA KAZUHIKO
IPC分类号： G11C7/06 , G11C11/4091 , H01L27/108 , G11C11/24
CPC分类号： G11C11/4091 , G11C7/065 , H01L27/10805
摘要： There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.
摘要翻译：产生相对于电源电压具有差异的第一内部电压，该差基本上等于动态存储单元的地址选择MOSFET的阈值电压。第一电压作为其高级侧的工作电压被提供给读出放大器。产生相对于电路接地电位具有预定差异的第二内部电压。第二电压作为低电平侧的工作电压提供给读出放大器。通过写放大器产生具有对应于第一内部电压的高电平和对应于第二内部电压的低电平的写入信号，以将其传送到连接到动态存储单元的一对互补数据线。高电平，例如表示选择电平和低电平的电源电压，例如指示非选择电平的电路接地电平被提供给连接到动态存储器单元的字线。

9. 发明授权

US6288967B2 Semiconductor integrated circuit device 有权
公开(公告)号：US6288967B2
公开(公告)日：2001-09-11
申请号：US74207800
申请日：2000-12-22
申请人： HITACHI LTD
发明人： FUJISAWA HIROKI , KAJIGAYA KAZUHIKO , FUKUI KENICHI , TACHIBANA TOSHIKAZU
IPC分类号： H01L21/8242 , G11C5/14 , G11C11/407 , H01L27/108 , G11C7/00
CPC分类号： G11C5/147
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

10. 发明专利

DE69718129D1 未知
公开(公告)号：DE69718129D1
公开(公告)日：2003-02-06
申请号：DE69718129
申请日：1997-10-27
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO , KAJIGAYA KAZUHIKO , MIYAZAKI YOSHIHIRO
IPC分类号： G05B9/03 , G06F11/00 , G06F11/16 , G06F11/18

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