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    • 10. 发明专利
    • RIVER INFORMATION PROCESSOR
    • JPH02181255A
    • 1990-07-16
    • JP34789
    • 1989-01-06
    • HITACHI LTD
    • TSUJIKAWA AKIOTERADA YASUHIRO
    • G06F15/16G06F15/177G06F19/00
    • PURPOSE:To cut the response time down to 1/2 compared with a case where a single arithmetic processor has a response in case plural requests are received at one time by using two arithmetic processors respond to the terminal requests in a non-data collection time band. CONSTITUTION:The data on a river are received by a communication controller 1, and an arithmetic processor 3 connected to the controller 1 via a switch device 2 inputs the data to write and store them into two data store devices 4. Then two arithmetic processors 3 receive the requests from the terminal equipments 5 via a multi-access constitution 8 and take the requested data out of the devices 4 to output them to the equipment 5. Each processor 3 contains four states, i.e., a stop state, a single operation state, a double device operation (primary) state, and double operation (secondary) state. When the processor 3 is started, the operating state of the other system is confirmed via a mutual communication mechanism 6. In case the other system has no operation, the controller 1 is connected to its own system (single operation state). While the double device operation (secondary) state is set in case the other system is already operated.