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1. 发明专利

JPS6221308A MUTING CIRCUIT 失效
公开(公告)号：JPS6221308A
公开(公告)日：1987-01-29
申请号：JP16025485
申请日：1985-07-22
申请人： HITACHI TOBU SEMICONDUCTOR LTD , HITACHI LTD
发明人： TSUCHIYA KENICHI , TAKESHITA RITSUJI
IPC分类号： H03F1/00
摘要： PURPOSE:To decrease undesired noise at power supply and malfunction by using a muting circuit turned on by detecting the leading of a voltage level at power application and releasing the on-state corresponding to the supply of a muting signal so as to interrupt the signal transmission path. CONSTITUTION:When a Vcc power supply is applied, a current flows from a resistor R1 to a resistor R2 of the muting circuit 1, a transistor (TR) Q3 is turned off until a voltage level rises up to a prescribed level to turn on a TR Q21 of a detection circuit 3 and a TR Q51 of a muting circuit 5. When the TR Q51 is turned on, the voltage is dropped by a resistor R51, the bias voltage of a TR Q55 is cut off and the TR Q55 is turned off. A TR Q52 is turned on to keep a current to the resistor R51 and this state is continued. Further, TRs Q54, Q55 are turned on. Thus, undesired noise generation and transmission at power application is reduced.

2. 发明专利

JPS61281709A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS61281709A
公开(公告)日：1986-12-12
申请号：JP12252385
申请日：1985-06-07
申请人： HITACHI TOBU SEMICONDUCTOR LTD , HITACHI LTD
发明人： TSUCHIYA KENICHI , TAKESHITA RITSUJI
IPC分类号： H03F1/34 , H03F3/343 , H03F3/45
摘要： PURPOSE:To obtain an output signal in response to the leading of an input signal from OV by constituting an amplifier to which an input signal is applied by PNP transistor (TR). CONSTITUTION:The PNP TRs Q1, Q2 constitute an amplifier. TRs Q3, Q4 reduce an offset voltage of TRs Q1, Q2. Further, a reference voltage Vref, TRs Q5, Q6 and resistors R4, R5 constitute a constant current circuit. A voltage V1 is an input signal to the amplifier and when the voltage level of the voltage V1 rises from OV, the voltage VA rises in response to the level change. Then the voltage VB also rises, a TR Q7 is turned on to feed back negatively a current in response to the level change of the voltage V1 to a base of the TR Q2 via a diode D1. An output signal V0 is obtained by the voltage drop of a resistor R6 and stabilized by a capacitor C1.

3. 发明专利

JPS61253906A CURRENT MIRROR CIRCUIT 失效
公开(公告)号：JPS61253906A
公开(公告)日：1986-11-11
申请号：JP9550985
申请日：1985-05-07
申请人： HITACHI TOBU SEMICONDUCTOR LTD , HITACHI LTD
发明人： TSUCHIYA KENICHI , WATANABE TOSHIHIKO
IPC分类号： H03F3/343 , H03F3/347
摘要： PURPOSE:To reduce an oscillating phenomenon by forming a feedback circuit for superposing a feedback current from respective bases of a pair of pnp transistor (TR) to a reference current through an amplifier and a resistor for controlling gain. CONSTITUTION:When the reference current I1 determined by a constant current circuit CS1 flows into a current mirror circuit consisting of the pnp TRs Q1, Q2, an output current I2 flows into the TR Q2 and a load circuit RL. The current of IbQ1+IbQ2 flows into the resistor R1 and a current fed back from the base of a TR Q3 to the collector of the TR Q1, i.e. to the current course of the reference current I1, is determined by IbQ1+IbQ2/hFEQ3. The emitter resistance reQ3 of the TR Q3 is increased by connecting the resistor R1 and the gain of a closed loop circuit which is the current course of the feedback current is reduced. Consequently, the oscillation phenomenon is reduced.

4. 发明专利

JPS5979616A Buffer amplifier 失效
标题翻译：缓冲放大器
公开(公告)号：JPS5979616A
公开(公告)日：1984-05-08
申请号：JP18918882
申请日：1982-10-29
申请人： Hitachi Ltd , Hitachi Tobu Semiconductor Ltd
发明人： TSUCHIYA KENICHI , SATOU TETSUO
IPC分类号： H03F3/50 , H03F3/34
摘要： PURPOSE: To vary idling current by the amplitude of an input signal and to prevent the generation of offset voltage by providing the titled amplifier with a detecting circuit to detect the amplitude of the input signal and a control circuit to control current in accordance with the current flowing into the detecting circuit.
CONSTITUTION: When an input signal V
in has positive polarity and the amplitude is increased/decreased, the current flowing into a transistor (TR) Q
2 is increased/decreased in accordance with the size of the signal and the current flowing into TRs Q
5 , Q
6 is also increased/decreased. When the emitter voltages of TRs Q
2 , Q
4 are raised, the TR Q
4 is turned off, but TRs Q
7 ∼Q
10 operate and the current corresponding to the amplitude of the input signal V
in flows into a TR Q
10 . Independently of the size of the amplitude of the input signal V
in , respective base voltages of TRs Q
1 , Q
3 are made uniform at the almost same voltage level and the voltage difference (offset voltage) does not appear between the base voltages. When the input signal has negative polarity, the TRs Q
1 , Q
2 are turned off, the TR Q
4 is turned on by the TR Q
7 and then the current flowing into the Q
4 flows into the base of the TR Q
5 . Thereafter, the TRs operate in the same manner as the case of the positive polarity. Thus idling current can be controlled in accordance with the amplitude of the input signal, so that useless power consumption can be prevented.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过输入信号的幅度来改变空载电流，并通过为标称放大器提供检测电路来检测输入信号的幅度以及控制电路根据电流来控制电流来防止产生失调电压流入检测电路。构成：当输入信号Vin具有正极性并且幅度增加/减小时，流入晶体管（TR）Q2的电流根据信号的大小增加/减小，流入TRs的电流Q5，Q6为也增加/减少。当TRs Q2，Q4的发射极电压升高时，TR Q4截止，而TRs Q7-Q10工作，与输入信号Vin的幅度对应的电流流入TR Q10。独立于输入信号Vin的振幅的大小，TRs Q1，Q3的各个基极电压在几乎相同的电压电平下均匀，并且在基极电压之间不出现电压差（偏移电压）。当输入信号为负极性时，TR Q1，Q2截止，TR Q4由TR Q7导通，流入Q4的电流流入TR Q5的基极。此后，TR以与正极性相同的方式工作。因此，可以根据输入信号的幅度来控制空转电流，从而可以防止无用的功耗。

5. 发明专利

JPH04131977A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04131977A
公开(公告)日：1992-05-06
申请号：JP25457890
申请日：1990-09-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： TSUCHIYA KENICHI , SAKOSHITA KAORU , SAKAKIBARA YASUHIRO , KOMABAYASHI HISASHI
IPC分类号： G06F15/78 , H01L21/822 , H01L27/04
摘要： PURPOSE:To extend operating range by switch-controlling so as to be an on state when it is an input mode by a control signal formed corresponding to the operating mode and to be an off state when it is the operating mode that large voltage is impressed on an input/output terminal at least. CONSTITUTION:When it is a large voltage output mode, an MOSFET for clamping Q3 is made to be an off state by a mode determining circuit MODE. Accordingly, since an input/output terminal I/O to which large voltage is outputted and input buffers IB1 and IB2 are separated electrically, the withstand voltage break-down of an element owing to the large voltage can be prevented. Then, when the input/output terminal I/O is used for an input mode, the MOSFET for clamping Q3 is made to be an on state by the mode determining circuit MODE. Thus, since the MOSFET for clamping Q3 is made to be the on state when it is the large voltage output mode, the sure protection of an input circuit is attained and since the MOSFET for clamping Q3 is made to be the on state when it is an input mode, the high speed fetching of an input signal is attained.

6. 发明专利

JPS5764941A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS5764941A
公开(公告)日：1982-04-20
申请号：JP14045980
申请日：1980-10-09
申请人： Hitachi Ltd
发明人： TSUCHIYA KENICHI
IPC分类号： H01L23/52 , H01L21/60 , H01L21/82 , H01L27/118
CPC分类号： H01L2224/05554 , H01L2224/48245 , H01L2224/48247 , H01L2224/49 , H01L2924/01082 , H01L2924/14 , H01L2924/00012
摘要： PURPOSE:To enable modification of a circuit without altering a wiring pattern in an IC of the type altering the circuit by the connection or disconnection of a part of wires by providing pads at the wire units of the circuit and altering the circuit existence or absence of a wire bonding. CONSTITUTION:When the type of the output FET(Q1) of a circuit is selected to a load FET(Q2) built-in type or an open drain type, bonding pads BP1, BP2 are respectively provided at the drain terminal side of the Q1 and the terminal of the Q2. When only the pad BP1 is connected to an external lead OL via a wire W1, it becomes the open drain type. When the pad BP2 is also connected to the OL, it becomes the load built-in type. Similarly, the circuit may be altered according to whether a direct wire bonding is performed or not between the pads BP1 and BP2. In this manner the alteration of the circuit in the manner slicing type may be performed merely by the presence or absence of the wire bonding, thereby enabling the shortening of the developing period of time and the reduction of the expense.
摘要翻译：目的：通过在电路的线路单元处设置焊盘并改变电路的存在或不存在来改变电路的修改，而不改变通过连接或断开一部分电线来改变电路类型的IC的布线图案引线键合。构成：当将电路的输出FET（Q1）的类型选择为内置型负载FET（Q2）或开漏型时，在Q1的漏极端侧分别设置接合焊盘BP1，BP2 和Q2的终端。当只有焊盘BP1经由导线W1连接到外部引线OL时，它变成开漏型。当焊盘BP2也连接到OL时，它成为负载内置型。类似地，可以根据在焊盘BP1和BP2之间是否执行直接引线接合来改变电路。以这种方式，可以仅通过引线接合的存在或不存在来执行切片类型的电路的改变，从而能够缩短显影时间段和降低费用。

7. 发明专利

JPS5853072A RAM DEVICE 失效
公开(公告)号：JPS5853072A
公开(公告)日：1983-03-29
申请号：JP14943281
申请日：1981-09-24
申请人： HITACHI LTD
发明人： ABE HIROYUKI , HOTSUTA SHINKICHI , TSUCHIYA KENICHI
IPC分类号： G11C11/41 , G06F12/00 , G11C7/00
摘要： PURPOSE:To make the program forming easy, by providing flags corresponding to a plurlaity of display data stored in an RAM area, and rewriting the flags with the program, and displaying display data of specified types. CONSTITUTION:An area of an RAM3 is divided into an X type display area 3A and Y type display area 3B and a flag set device 3 in 1-bit setting flags of ''1'', ''0'' is provided and the setting of flag is set with a program. Operation data from a computer is stored in a vacant area. Thus, display data of specified kinds can be displayed, no data rewrite at the change of display is done and the degree of freedom for RAM display area can be increased.

8. 发明专利

JPS52104010A DRIVING SYSTEM FOR LOAD SIDE DEVICE ELECTRONIC EXCHANGER 失效
公开(公告)号：JPS52104010A
公开(公告)日：1977-09-01
申请号：JP1993476
申请日：1976-02-27
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： SEKI SHIGEO , YOSHIDA HIRONOBU , HATAKEYAMA HIDEHISA , KANEDA YOSHIHITO , YANAGIDA AKIRA , MUNAKATA KOUICHI , KAWATANI IKUO , TANABE SENICHI , SETO HAJIME , TSUCHIYA KENICHI
IPC分类号： H04Q1/20 , H04Q3/545
摘要： PURPOSE:To prevent the delay of normal operation of a system, by means of making the drive system usable even if in the case of load side trouble.

9. 发明专利

JPS6180906A Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：JPS6180906A
公开(公告)日：1986-04-24
申请号：JP20178084
申请日：1984-09-28
申请人： Hitachi Ltd , Hitachi Tobu Semiconductor Ltd
发明人： SATO TETSUO , TSUCHIYA KENICHI
IPC分类号： H03F1/34 , H03F3/45
CPC分类号： H03F3/45071
摘要： PURPOSE:To make a phase capacitor and a DC cut capacitor unnecessary, and to improve a degree of integration of an IC by using an amplifier circuit as a composite differential circuit of a - power source consisting of a differential amplifier stage and an emitter follower stage. CONSTITUTION:The titled circuit is constituted so that an emitter follower stage consisting of a transistor (TR) Q5 which has connected an output load R1 to an emitter is provided on the next stage of a differential amplifier constituted of TRs Q1 and Q2, an output Vout is fetched from the emitter follower stage, and also this output is brought to a negative feedback to the other input terminal of the differential amplifier, and it is operated by a power source + Vcc. As a result, an open loop voltage gain of an amplifier circuit becomes small, and an oscillation preventing capacitor becomes unnecessary. Also, the negative feedback is executed through the emitter follower, therefore, a DC cutting capacitor of the differential amplifier becomes unnecessary, and a degree of integration of an IC can be improved.
摘要翻译：目的：为了使相位电容器和直流切割电容器不必要，并且通过使用放大器电路作为由差分放大器级和射极跟随器级组成的电源的复合差分电路来提高IC的集成度。构成：标题电路被构造成使得由将输出负载R1连接到发射极的晶体管（TR）Q5组成的射极跟随器级设置在由TR Q1和Q2构成的差分放大器的下一级上，输出 Vout从射极跟随器级获取，并且该输出也被送到差分放大器的另一输入端的负反馈，并由电源+ Vcc操作。结果，放大器电路的开环电压增益变小，并且不需要防振荡电容器。此外，通过射极跟随器执行负反馈，因此，不需要差分放大器的DC切割电容器，并且可以提高IC的集成度。

10. 发明专利

JPS5852834A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5852834A
公开(公告)日：1983-03-29
申请号：JP15060581
申请日：1981-09-25
申请人： HITACHI LTD
发明人： TSUCHIYA KENICHI
IPC分类号： H01L21/603 , H01L21/60
摘要： PURPOSE:To prevent disconnection of wire between a semiconductor element and a lead to be generated when an integrated circuit device is to be assembled and to be sealed by a method wherein the fixing part by pressure of a bonding wire to connect the semiconductor element and a lead frame is fixed with a covering bump. CONSTITUTION:By fixing the fixing part by pressure of the bonding wire with the covering bump 4, disconnection and strip off of the wire 1 are negated, tensile strength on the whole of wire is enlarged, and DC disconnection fault to be generated between the element and the lead can be eliminated. The bump 4 is formed of an insulator or a metal of comparatively high melting point and having intensity. Accordingly disconnection of wire to be generated between the element and the lead can be eliminated, and DC fault can be reduced.

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