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1. 发明专利

JP2003242190A FLOOR PLAN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2003242190A
公开(公告)日：2003-08-29
申请号：JP2002044112
申请日：2002-02-21
申请人： HITACHI LTD
发明人： YAMADA HIROMITSU , SHIGEGAKI MASATO
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a floor plan method capable of exactly estimating wiring length and wiring congestion degree. SOLUTION: By designating the position of a block in a region unit in which a chip flat surface is divided into grid shapes and arranging a logic element virtually generated in the divided unit region, the wiring length and the wiring congestion degree are accurately estimated. COPYRIGHT: (C)2003,JPO

2. 发明专利

JP2003132109A FLOOR PLAN METHOD AND FLOOR PLAN DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2003132109A
公开(公告)日：2003-05-09
申请号：JP2001323708
申请日：2001-10-22
申请人： HITACHI LTD
发明人： HARUMA TOSHIYUKI , SHIGEGAKI MASATO
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To solve a problem of being unable to easily make a floor plan for requiring much processing time when manually performing a series of this work since an optional shape block frequently requires a shape change or a movement of blocks by the overlapping occurrence with the other blocks at a movement destination even if the optimal movement direction is obtained by making a delay change calculation by virtually moving the blocks. SOLUTION: A region of the respective blocks is set in a region unit of dividing a chip in a grating shape, and the region is determined by expanding the region so as to minimize an increase quantity of the boundary length up to balancing pressure in a boundary with a value of dividing the required area by the region area as the pressure.

3. 发明专利

JP2003016126A Cell arrangement method for semiconductor integrated circuit 审中-公开
标题翻译：用于半导体集成电路的单元布置方法
公开(公告)号：JP2003016126A
公开(公告)日：2003-01-17
申请号：JP2001196497
申请日：2001-06-28
申请人： Hitachi Ltd , Hitachi Software Eng Co Ltd , 日立ソフトウエアエンジニアリング株式会社 , 株式会社日立製作所
发明人： SAKAGAMI TOMONARI , SHIGEGAKI MASATO , YAMADA HIROMITSU , MIZUTANI KAZUHIRO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a cell arrangement method for a semiconductor integrated circuit, that can shorten delay and wire length by reducing the number of critical nets.
SOLUTION: A logic file and a library are inputted first of all, and cells, in which the number of terminals constituting a net and the number of input/ output terminals of cells constituting the net are two respectively, and the total of the widths of the cells constituting the net is not longer than a given, are extracted as a cell group candidate (301 and 302). In the case there are candidate cells, cell groups for cell grouping candidates are ranked with the driving performance rates of the cells that are a candidate, the number of input/output terminals to be reduced by grouping and the number of pins for the cells to be grouped as evaluation values (303 and 304). Then, grouping processing is applied to grouping candidate cell groups in accordance with the obtained ranking to return to processing from the step 302 (305). When all the candidate cells are processed and no candidate cell retains in check of the step 303, a grouped cell is handled in the same manner as that of a normal cell to be subjected to arrangement processing (306).
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种用于半导体集成电路的电池布置方法，其可以通过减少关键网的数量来缩短延迟和电线长度。解决方案：首先输入逻辑文件和库，并且其中构成网络的终端的数量和构成网络的小区的输入/输出端子的数量的单元分别为两个，构成网络的小区不长于给定的小区被提取为小区组候选（301和302）。在存在候选小区的情况下，将用于小区分组候选的小区组作为候选的小区的驱动性能率，通过分组减少的输入/输出终端的数量和小区的引脚数量被分组为评估值（303和304）。然后，根据获得的排序将分组处理应用于分组候选小区组，以返回到步骤302（305）的处理。当处理所有候选小区并且没有候选小区保留步骤303的检查时，以与要进行布置处理的正常小区相同的方式处理分组小区（306）。

4. 发明专利

JPS6361370A LSI CHIP LAYOUT SUPPORTING DEVICE 失效
公开(公告)号：JPS6361370A
公开(公告)日：1988-03-17
申请号：JP20367186
申请日：1986-09-01
申请人： HITACHI LTD
发明人： SHIGEGAKI MASATO
IPC分类号： H01L21/82 , G06F17/50 , H01L21/822 , H01L27/04
摘要： PURPOSE:To realize the minimization and equalization of the delay of a main signal and the minimization of a chip area by first designating a channel in which the main signal flows and arranging parts along the channel, at the time of executing the layout. CONSTITUTION:To an information processor 4, a display device 1, a character input device 2, a coordinate input device 3 and a memory device 5 are connected and a layout supporting device is constituted. At the time of executing a layout, a layout screen 12 and a signal listing-up screen are displayed on the display device 1 and first, by using the coordinate input device 3, a channel 14, in which a main signal flows, is designated. Next, along the channel 14, parts 18 are arranged in the layout screen 12.

5. 发明专利

JP2007140906A Method and system for trading information processing performance 审中-公开
标题翻译：交易信息处理性能的方法和系统
公开(公告)号：JP2007140906A
公开(公告)日：2007-06-07
申请号：JP2005333817
申请日：2005-11-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HIRASAWA MITSURU , KOMIYA HIROSHI , OTOSE MICHIKO , SHIGEGAKI MASATO
IPC分类号： G06F9/50 , G06Q30/06 , G06Q50/00 , G06Q50/10
摘要： PROBLEM TO BE SOLVED: To provide an information processing performance trading system for measuring a processing time and calculating use charge in consideration of a processing time limit, information processing performance, and a limited cost of a site to receive the information processing performance, as well as the information processing performance and a schedule of a site to provide the information processing performance according to the above trade request information. SOLUTION: In the information processing performance trading system, the information processing performance trade request information of the information processing performance receiving site 108 is transmitted to an information processing performance trading site 101 for mediating the trade of information processing performance between an information processing performance receiving site 108 and an information processing performance providing site 11, which assigns information processing performance providing sites 117 and 118 based on the trade request information of the information processing performance receiving site 108, to transmit the result of processing in the information processing performance providing sites 117 and 118 to the information processing performance receiving site 108. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种信息处理性能交易系统，用于测量处理时间并考虑处理时间限制，信息处理性能和接收信息处理性能的站点的有限成本来计算使用费用以及根据上述交易请求信息提供信息处理性能的站点的信息处理性能和时间表。解决方案：在信息处理性能交易系统中，信息处理性能接收站点108的信息处理性能交易请求信息被发送到信息处理性能交易站点101，用于中介信息处理性能的交易性能接收站点108和信息处理性能提供站点11，其基于信息处理性能接收站点108的交易请求信息来分配信息处理性能提供站点117和118，以将处理结果发送到信息处理性能提供站点117和118到信息处理性能接收站点108.版权所有：（C）2007，JPO＆INPIT

6. 发明专利

JP2001229218A LOGICAL SYNTHESIS SYSTEM 失效
公开(公告)号：JP2001229218A
公开(公告)日：2001-08-24
申请号：JP2000043532
申请日：2000-02-16
申请人： HITACHI LTD
发明人： ADACHI KAZUHIRO , SHIGEGAKI MASATO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a logical synthesis system capable of preventing a delay constraint violation of layout results without postponing the design time by making the difference between a wiring length assumed at the time when a logical synthesis is performed and the real wiring length of the layout results small. SOLUTION: This system has a means dividing a synthetic object block into a plurality of subblocks in the case of performing logical synthesis, a means deciding a floor plan inside the synthetic object block of the divided subblocks, a means individually calculating a wiring length inside each block, a means individually calculating a wiring length between subblocks from the floor plan, means individually calculating delay on the basis of the calculated wiring lengths, a logically optimizing means on the basis of the delay calculation results, and a means outputting the divided subblocks and the floor plan.

7. 发明专利

JP2000222526A PEN INPUT METHOD, PEN INPUT DEVICE, AND INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JP2000222526A
公开(公告)日：2000-08-11
申请号：JP2000021057
申请日：2000-01-31
申请人： HITACHI LTD
发明人： FUTAKI SEIJI , KOJIMA KEIJI , MATSUDA YOSHIKI , KITAHARA YOSHINORI , SHIGEGAKI MASATO
IPC分类号： G06F15/02 , G06F17/21 , G06K9/62
摘要： PROBLEM TO BE SOLVED: To enable a user to easily use a pen input computer system without special knowledge. SOLUTION: The pen input computer system A is provided with a portable pen input device 104, which is provided with a storage means 106 for storage of user peculiar information and a pen interface device 107 which gives this user peculiar information to a computer system main body 101, and he computer system main body 101 which interprets pen operation by a user peculiar information given from the portable pen input device 104 through the interface device 103. By this constitution, it is unnecessary to read a flexible disk where an operation interpretation dictionary peculiar to a user is written. The operation to set the pen operation circumstances is made unnecessary or is facilitated.

8. 发明专利

JPH0950446A WIRING DISPLAY METHOD 失效
公开(公告)号：JPH0950446A
公开(公告)日：1997-02-18
申请号：JP20066695
申请日：1995-08-07
申请人： HITACHI LTD
发明人： SHIGEGAKI MASATO , NAKAJIMA HIROYUKI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To easily recognize the congestion degree of wiring in the case of a reduction display and to perform display at a high speed by displaying the wiring thinner than a pixel probabilitically. SOLUTION: The wiring thinner than the pixel is plotted with a probability proportional to the thinness on a display screen. That is, when the wiring is thinner than the pixel, the wiring is plotted with lower probability when the wiring width is thinner and with higher probability when it is thicker. As the easiest plotting probability, a method for taking the wiring width itself for the probability when the wring width is 1 or less than 1 can be mentioned. A monotone increase function for which generally it is 0 when the wiring width is 0 and it is 1 when it is 1 or more than 1 is sufficient. It is empirically obtained that the larger part of processing time is spent within a plotting routine in normal graphic display. Thus, when the number of times that the plotting routine is called is less, the processing time is shortened that mach. By this method, the number of times when the plotting routine is called is actually reduced and the display speed is accelerated compared to the case of plotting all the wiring.

9. 发明专利

JPS61267344A CHIP LAYOUT METHOD FOR LSI 失效
公开(公告)号：JPS61267344A
公开(公告)日：1986-11-26
申请号：JP10811385
申请日：1985-05-22
申请人： HITACHI LTD
发明人： SHIGEGAKI MASATO , MIURA JIHEI
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/02 , H01L27/04
摘要： PURPOSE:To sufficiently reduce useless regions by a method wherein a proper combination of random logical block dimensions is chosen by using a linear programming method for a reduced chip area when the required width is estimated of a wiring region between blocks arranged relative to each other. CONSTITUTION:In view of the relations between the relative positioning of given blocks and logical connections, the minimum width required is estimated for a wiring region between blocks, the blocks are properly arranged with consideration given to the width of wiring regions between the blocks, and then wiring is accomplished between the blocks for the completion of chip layout. As a method for selecting a proper block layout out of many candidates different from each other in width and height, linear relations in terms of coordinates and dimensions are utilized for the determination of conditions whereunder the necessary width is secured of wiring regions, and the conditions for designating a block layout candidate is expressed in linear conditions covering the region including proper block dimensions. A problem is solved involving a linear program for the minimization of a target function expressed in the form of a combination of chip width and height, whereby the area occupied by chips is reduced to the minimum.

10. 发明专利

JP2002007136A SYSTEM FOR AUTOMATICALLY DISTRIBUTING SOFTWARE 失效
公开(公告)号：JP2002007136A
公开(公告)日：2002-01-11
申请号：JP2000192682
申请日：2000-06-22
申请人： HITACHI LTD
发明人： FURUYAMA AKIRA , SHIGEGAKI MASATO
IPC分类号： G06F15/16 , G06F9/445 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To store the minimum necessary files into the disk of a client computer in order to reduce the usage of the disk to the minimum, and to reduce a load on a network. SOLUTION: This system is provided with a means for; automatically detecting a file necessary at the time of executing software at a client side; judging whether the file is already stored in the storage area of its own computer; and automatically obtaining the file from a distributing server when it is necessary.

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