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1. 发明专利

DE69840039D1 未知
公开(公告)号：DE69840039D1
公开(公告)日：2008-11-06
申请号：DE69840039
申请日：1998-01-27
申请人： HITACHI LTD
发明人： SAWADA HIDEO , ARAI IKUYA , KABUTO NOBUAKI , KITO KOJI , KIKUCHI KAZUFUMI , IWABUCHI KAZUNORI , SAITO KENICHI
IPC分类号： G09G5/30 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/14 , G09G5/18 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395

2. 发明专利

GB2132797A SYSTEM FOR DETECTING ACCESS TO STORAGE 未知
公开(公告)号：GB2132797A
公开(公告)日：1984-07-11
申请号：GB8329748
申请日：1983-11-08
申请人： HITACHI LTD
发明人： YATA KIYOSHI , SAWADA HIDEO
IPC分类号： G06F11/34 , G06F11/36 , G06F12/10
摘要： A system for detecting access to a storage in a data processing apparatus which includes an address translation look-aside buffer which holds a part of an address translation table listing correspondences between logical addresses and real addresses, entry of the translation look-aside buffer being referred to upon every access to the storage. Each of the entries is added with information bit indicating whether a storage region corresponding to a given entry includes an area which is allocated for the detection of the access to the storage. Detection as to whether an address for accessing the storage is located within the area allocated for the access detection is not carried out when the identification information indicates that the storage region to be accessed does not include the area allocated for the access detection.

3. 发明专利

DE3340956A1 未知
公开(公告)号：DE3340956A1
公开(公告)日：1984-05-24
申请号：DE3340956
申请日：1983-11-11
申请人： HITACHI LTD
发明人： YATA KIYOSHI , SAWADA HIDEO
IPC分类号： G06F11/34 , G06F11/36 , G06F12/10 , G06F11/28 , G06F9/34 , G06F13/06 , G11C29/00
摘要： A system for detecting access to a storage in a data processing apparatus which includes an address translation look-aside buffer which holds a part of an address translation table listing correspondences between logical addresses and real addresses, entry of the translation look-aside buffer being referred to upon every access to the storage. Each of the entries is added with information bit indicating whether a storage region corresponding to a given entry includes an area which is allocated for the detection of the access to the storage. Detection as to whether an address for accessing the storage is located within the area allocated for the access detection is not carried out when the identification information indicates that the storage region to be accessed does not include the area allocated for the access detection.

6. 发明专利

DE3379556D1 DATA PROCESSING APPARATUS FOR VIRTUAL MEMORY SYSTEM 未知
公开(公告)号：DE3379556D1
公开(公告)日：1989-05-11
申请号：DE3379556
申请日：1983-01-28
申请人： HITACHI LTD
发明人： SAWADA HIDEO , YATA KIYOSHI
IPC分类号： G06F12/04 , G06F12/10 , G06F12/02
摘要： A data processing apparatus for a virtual memory system including a logical address register (1), a real address register (2), a paged address translation table (3) and an address translation buffer (4) in which a map of a fraction of the paged address translation table is stored columnwise. Upon checking address translatability of a logical address into a real address, a bit (C) of a translation control word contained in the column of the address translation buffer (4) relevant to that logical address indicates whether or not a succeeding logical address is susceptible to the address translation. Necessity to pretest the address translatability of every logical address is obviated. System overhead is considerably reduced.

7. 发明专利

GB2116757B DIVISION APPARATUS 未知
公开(公告)号：GB2116757B
公开(公告)日：1985-12-11
申请号：GB8301620
申请日：1983-01-21
申请人： HITACHI LTD
发明人： SAWADA HIDEO
IPC分类号： G06F7/493 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/535 , G06F7/54
摘要： A division apparatus. A quotient of one digit and a remainder are determined by repeating execution of a single type processing of adding an integral multiple of a divisor and an intermediate remainder. The apparatus includes first, second and third registers for storing a dividend or the intermediate remainder, the integral multiple of a divisor and a carry resulted from a preceding operation, respectively, a selection circuit for selecting the complement of the integral multiple of the divisor when the carry is zero while selecting the integral multiple of the divisor when the carry is 0, an arithmetic circuit for performing adding operation on the output of the selection circuit and the content of the first register with the carry being served as the initial carry, and a counter for counting a number which corresponds to the integral multiple of the divisor. The result of the arithmetic operation which is executed in dependence on the value assumed by the carry is placed in the first register. The quotient is determined on the basis of the content of the counter.

10. 发明专利

GB2132797B SYSTEM FOR DETECTING ACCESS TO STORAGE 未知
公开(公告)号：GB2132797B
公开(公告)日：1986-02-19
申请号：GB8329748
申请日：1983-11-08
申请人： HITACHI LTD
发明人： YATA KIYOSHI , SAWADA HIDEO
IPC分类号： G06F11/34 , G06F11/36 , G06F12/10
摘要： A system for detecting access to a storage in a data processing apparatus which includes an address translation look-aside buffer which holds a part of an address translation table listing correspondences between logical addresses and real addresses, entry of the translation look-aside buffer being referred to upon every access to the storage. Each of the entries is added with information bit indicating whether a storage region corresponding to a given entry includes an area which is allocated for the detection of the access to the storage. Detection as to whether an address for accessing the storage is located within the area allocated for the access detection is not carried out when the identification information indicates that the storage region to be accessed does not include the area allocated for the access detection.

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