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    • 9. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH10335642A
    • 1998-12-18
    • JP14742597
    • 1997-06-05
    • HITACHI LTDHITACHI TOBU SEMICONDUCTOR LTDHITACHI MICROCOMPUTER SYST
    • MARUYAMA YASUONAKURA KENICHISATO TAKAHIRONAGANO HIROMI
    • H01L29/78
    • PROBLEM TO BE SOLVED: To prevent increase of source wiring resistance which is caused by increase of length of stripes, by forming conductor layers which brings an electrode conductor layer in continuity with a source leading-out wiring connected with a source region, on a semiconductor substrate in the respective stripe parts. SOLUTION: A source leading-out wiring 10 connected with the source region 8 of an MISFET has a continuity with a substrate conductor layer 1, in a linkage part, through a connecting layer 12 formed in a semiconductor substrate. The substrate conductor layer 1 has a continuity with a source electrode 13 formed on the back of the substrate conductor layer 1 as a facing surface of the semiconductor substrate main surface, and an electrode conductor layer is constituted of the source electrode 13 and the substrate conductor layer 1. The source leading-out wiring 10 and the substrate conductor layer 1 are connected, in the respective stripe parts, through conductor layers 14 formed on the semiconductor substrate between the respective cells of the respective stripe parts divided into a plurality of cells. Thereby increase of source wiring resistance which is to be caused by increase of length of the stripes can be prevented.
    • 10. 发明专利
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF
    • JPH04122062A
    • 1992-04-22
    • JP24336890
    • 1990-09-12
    • HITACHI LTDHITACHI MICROCUMPUTER ENG
    • NAGANO HIROMINIINO KAORUSHIGEMATSU TAKUSHINDO YOSHIMI
    • H01L27/082H01L21/8228
    • PURPOSE:To increase a junction dielectric strength of a bi-polar transistor and to reduce malfunctions thereof by injecting a smaller amount of p-type impurity than that of n-type impurity into a surface layer of an n -type buried semiconductor region for setting an impurity density of the surface layer on the p-type collector region side low. CONSTITUTION:A pnp-type bi-polar transistor Tr1 is mounted on a principal plane of a p-type semiconductor substrate 1 through an n -type buried semiconductor region 3, an element isolation region. An impurity density of a p-type collector region (p -type buried semiconductor region 4) of the Tr1 being set high, an impurity density of a surface layer 11 of the region 3, an element isolation region, which has a junction with the p-type collector region, is set low. Processes included are a process in which an n-type impurity is injected to the principal plane of the substrate 1 to form the region 3, an element isolation region, and a process in which a smaller amount of p-type impurity 11p than that of the n-type impurity is injected to the surface layer 11 of the region 3 for setting an impurity density of the surface layer 11 on the region 4 side of the region 3 low. Consequently, a junction dielectric strength of the bi-polar transistor is increased whereas malfunctions are reduced.