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1. 发明专利

JP2003100745A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003100745A
公开(公告)日：2003-04-04
申请号：JP2001290143
申请日：2001-09-21
申请人： HITACHI LTD
发明人： MIYAZAKI HIROSHI
IPC分类号： H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a technique to prevent contamination caused by copper diffusion when copper infiltrates from the outer edge of a silicon wafer. SOLUTION: By introducing and diffusing aluminum on an area of the outer edge of the silicon wafer 50 where silicon is exposed, a highly concentrated aluminum-containing layer is formed. Gettering is performed with copper by an Al-Si alloy layer of the aluminum-containing layer, thus preventing diffusion of copper.

2. 发明专利

JP2002164428A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002164428A
公开(公告)日：2002-06-07
申请号：JP2000362462
申请日：2000-11-29
申请人： HITACHI LTD
发明人： OSHIMA TAKAFUMI , MIYAZAKI HIROSHI , AOKI HIDEO , OMORI KAZUTOSHI
IPC分类号： C23C16/42 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/8238 , H01L23/522 , H01L23/532 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of improving heat resistance of a dual damascene wiring and resistance to electromigration. SOLUTION: An interlayer insulating film 23 surrounding contact holes 26 for connecting a wiring 21 of a second wiring layer with a wiring 28 of a third wiring layer is constituted using the insulating material having relatively small Young's modulus compared with Young's modulus of the insulating material constituting the insulating film 25 surrounding the wiring groove 27.

3. 发明专利

JP2000323568A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000323568A
公开(公告)日：2000-11-24
申请号：JP13000299
申请日：1999-05-11
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SATO AKIRA , MIYAZAKI HIROSHI , FUKADA SHINICHI , AOKI HIDEO , OSHIMA TAKAFUMI
IPC分类号： H01L21/768 , H01L21/28
摘要： PROBLEM TO BE SOLVED: To reduce the dishing or erosion by removing a barrier metal film in wiring layer trenches formed into an insulation film and vias at lower parts thereof, etc., except their side walls, etc. SOLUTION: Wiring layer trenches 18 and vias 19 are formed into an insulation film on a semiconductor substrate 1 and a TiN barrier metal film 20 is deposited. Using the etch back method, this film 20 is etched back to remove the barrier metal film 20 on lower parts of the vias 19 and the surface, etc., of the insulation film, thereby forming a pattern of the barrier metal film 20 for side walls only in the trenches 18 and on the side walls of the vias 19 at the lower parts thereof. Wiring metal layers 21, 22 composed of Cu layers for seed layers are formed on a semiconductor substrate 1. This extremely reduces dishing and erosion and a high-performance and high-reliability semiconductor device can be manufactured.

4. 发明专利

JPH098036A WIRING STRUCTURE FOR SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH098036A
公开(公告)日：1997-01-10
申请号：JP14854595
申请日：1995-06-15
申请人： HITACHI LTD
发明人： HINODE KENJI , MIYAZAKI HIROSHI , TAKEDA KENICHI , FURUSAWA KENJI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PURPOSE: To obtain a highly efficient fine wiring for a semiconductor device which has small capacitance between wirings and is free from troubles in mechanical strength, dielectric strength, etc., by making a thickness of each part of high dielectric constant of an insulation layer formed in contact with a wiring side surface satisfy specific relation. CONSTITUTION: The device has a region 41 whose dielectric contact is lower than that of an insulation region formed in contact with a wiring side surface between adjacent wirings 32 in a part wherein the wirings of the same level formed on an insulation layer 22 formed in a semiconductor board surface or formed to be enclosed with insulation layers 22, 23 travel parallel adjacent each other. When a thickness in a wiring side surface of a region of high dielectric constant formed in contact with a wiring side surface is (a), a thickness measured from a wiring bottom is (b) and a thickness measured from a wiring upper surface is (c) in such a wiring structure, relation of b

5. 发明专利

JPH0729976A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0729976A
公开(公告)日：1995-01-31
申请号：JP17286293
申请日：1993-07-13
申请人： HITACHI LTD , HITACHI CHEMICAL CO LTD
发明人： FURUSAWA KENJI , MIYAZAKI HIROSHI , HONMA YOSHIO , MORISHIMA HIROYUKI
IPC分类号： H01L21/312 , H01L21/768 , H01L23/522
摘要： PURPOSE:To prevent an alkyl group of a side chain from being oxidized and then eliminated by oxygen plasma treatment by using a fluorosilicone resin film having a principal chain of siloxane bonding and a side chain of a fluoroalkyl group for an insulating film. CONSTITUTION:A first plasma oxide film 3 is formed on a lower-layer interconnection 2 formed on a semiconductor substrate 1. Nextly, a silanol oligomer liquid is applied and then it is heated and hardened in the nitrogen air flow to form a fluorosilicone resin film 4. After that, a second plasma oxide film 6 is formed and a connection hole 7 is made by lithography and dry etching. At that time, oxygen plasma treatment is conducted to remove resist. Then, an upper-layer interconnection 8 is formed. By this method, an alkyl group of a side chain is prevented from being oxidized and then eliminated by oxygen plasma treatment.

6. 发明专利

JPH0547654A SURFACE TREATING METHOD FOR SEMICONDUCTOR SUBSTRATE, MANUFACTURE OF SEMICONDUCTOR DEVICE AND SURFACE TREATING APPARATUS FOR CONDUCTING THE SAME 失效
公开(公告)号：JPH0547654A
公开(公告)日：1993-02-26
申请号：JP20046791
申请日：1991-08-09
申请人： HITACHI LTD
发明人： MIYAZAKI HIROSHI , HONMA YOSHIO
IPC分类号： G03F7/42 , H01L21/027 , H01L21/30 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/308
摘要： PURPOSE:To process a semiconductor substrate having copper or copper alloy almost without melting or changing properties of a thin film by bringing the substrate into contact with processing liquid containing proton donating or proton accepting organic solvent at a special temperature, and then holding it in oxidative substance and predetermined moisture atmosphere. CONSTITUTION:A semiconductor substrate 10 provided with a copper or copper allay film is dipped in processing liquid containing proton donative and proton acceptive organic solvent in a surface treating tank 31, and brought into contact with it at a higher temperature than the ambient temperature. After the contact, the substrate 10 is moved to a spare chamber 30 by a conveying mechanism 23. Since the chamber 30 holds the substrate 10 removed from the tank 31 for a desired time, it is held in an atmosphere containing 1000ppm or less of oxidative substance and moisture. Accordingly, deterioration of the film of the substrate 10 can be prevented.

7. 发明专利

JPH04283930A WIRING BOARD AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04283930A
公开(公告)日：1992-10-08
申请号：JP4640891
申请日：1991-03-12
申请人： HITACHI LTD
发明人： HONMA YOSHIO , HINODE KENJI , MIYAZAKI HIROSHI
IPC分类号： H01L21/306 , H01L21/3205 , H01L21/3213 , H01L21/66 , H01L21/768
摘要： PURPOSE:To furnish a structure in which a minute residue which is left after etching of a protective insulating (BPSG) film containing boron and phosphorus in the surface and causes a fault in nonvolatile memory LSI of 1 megabit or above, or the like, is removed in a wiring board comprising a semiconductor integrated circuit element etc., and to provide a manufacturing method thereof. CONSTITUTION:It is ascertained that a residue left on the surface of a BPSG film on the occasion of light etching of the film is element phosphorus contained in the BPSG film. Therefore, the residue left on the occasion when the film is light-etched with a liquid containing a fluoric acid is removed by etching it with a nitric acid, ammonia water or the like.

8. 发明专利

JPH04150022A PLASMA TREATMENT APPARATUS 失效
公开(公告)号：JPH04150022A
公开(公告)日：1992-05-22
申请号：JP27329890
申请日：1990-10-15
申请人： HITACHI LTD
发明人： MIYAZAKI HIROSHI , HONMA YOSHIO , MATSUMURA YASUHIDE , HARADA KUNIO , KONDO HITOSHI , SUZUKI ISAO
IPC分类号： H01L21/302 , H01L21/3065
摘要： PURPOSE:To ensure an etching apparatus which is excellent in a temperature response characteristic during a plasma discharge by a method wherein the heat capacity of an electrode is reduced, the heat conduction between a heat source and a substrate is increased and an uncertainty factor such as a thermal contact or the like is eliminated. CONSTITUTION:An electrode ceiling whose heat conduction is good and a cylindrical electrode side-plate which supports it and has a poor heat conduction are united by a welding operation; a groove 23 is formed along the circumference of a circle; an inner-face temperature distribution inside the electrode ceiling is made uniform. Fin-shaped grooves are carved in the rear of the electrode ceiling; a contact area with a gas is made wide. Supply electric power of a heater for gas heating use is kept constant; the opening degree of a flow- rate adjusting valve 26 is controlled automatically by using a PID controller 32; a gas which has been controlled to a prescribed temperature is blown form a nozzle; an electrode is heated or cooled. The heat capacity of the electrode plate is reduced, since forced convection is used, the problem of uncertainties such as a thermal contact state or the like is solved. Thereby, a temperature change during a plasma discharge can be suppressed to be small.

9. 发明专利

JPH0225023A FORMATION OF WIRING 失效
公开(公告)号：JPH0225023A
公开(公告)日：1990-01-26
申请号：JP17270888
申请日：1988-07-13
申请人： HITACHI LTD
发明人： MIYAZAKI HIROSHI , HINODE KENJI , HONMA YOSHIO , KOBAYASHI NOBUYOSHI
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/288 , H01L23/52
摘要： PURPOSE:To enable a fine Cu or Au wiring to be formed by using processed female forces comprising transition metal or compound thereof. CONSTITUTION:A connecting hole is made in an SiO2 film formed on an Si substrate 10. First, after depositing a TiN layer 12 as an auxiliary layer, a W layer 13 is deposited. Secondly, the layer 13 is etched away using an organic resist layer 14 as a mask. Thirdly, a Cu layer 15 is buried in as a conductor material by pulse-plating process using the layer 12 as one electrode. Fourthly, after removing the layer 14, the substrate 10 is hydrogen-annealed at 450-900 deg.C if necessary. Finally, the layers 13 and 12 as the female forces not covered with the layer 16 are removed. Through these procedures, a double layered submicron wiring comprising Cu and high melting point metal can be formed.

10. 发明专利

JPH01149423A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01149423A
公开(公告)日：1989-06-12
申请号：JP30750687
申请日：1987-12-07
申请人： HITACHI LTD
发明人： SUZUKI MASAYASU , MIYAZAKI HIROSHI , KOBAYASHI NOBUYOSHI , SAITO MASAYOSHI
IPC分类号： H01L21/3205 , C23C16/06 , H01L21/28 , H01L21/285 , H01L21/768
摘要： PURPOSE:To enable W, Mo around 1mum thick to be chemical-evaporated selectively thereby cutting down the frequency of device maintenance for improving the efficiency by a method wherein a chemically inert silylether group is substituted for a chemically active hydroxyl group on a substrate or inside a CVD furnace to perform surface processing. CONSTITUTION:When tungsten(W) or molybdenum(Mo) are filmed selectively on the surface of a conductor or semiconductor of a substrate including the surface of an insulator by chemical vapor deposition process(CVD process), a hydroxyl group on the surface of said substrate is to be substituted for silylether group. The insulator shall comprise either one of silicon oxide(SiO2), phosphorus glass(PSG), borophosphorus glass(BPSG), silicon nitride(Si2N4), oxysilicon nitride(SiOxNy). Besides, the semiconductor shall comprise either one of single crystal, silicon polycrystalline silicon, amorphous silicon and silicon germanium alloy. Furthermore, the thermal reaction of tungsten hexafluoride to hydrogen is to be used as the reaction of W-CVD while that of molybdenum hexafluoride to hydrogen is to be used as the reaction of Mo-CVD.

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