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1. 发明专利

DE3271101D1 A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A PROTECTION ELEMENT 未知
公开(公告)号：DE3271101D1
公开(公告)日：1986-06-19
申请号：DE3271101
申请日：1982-02-25
申请人： HITACHI LTD
发明人： YOSHIDA ISAO , OKABE TAKEAKI , KATSUEDA MINEO , NAGATA MINORU , MASUHARA TOSHIAKI , ASHIKAWA KAZUTOSHI , KATO HIDEAKI , ITO MITSUO , OHTAKA SHIGEO , MINATO OSAMU , SAKAI YOSHIO
IPC分类号： H01L27/02 , H01L27/04 , H01L27/06 , H01L29/78 , H01L29/861 , H01L23/56

2. 发明专利

DE10240342A1 未知
公开(公告)号：DE10240342A1
公开(公告)日：2003-05-22
申请号：DE10240342
申请日：2002-08-27
申请人： ELPIDA MEMORY INC , HITACHI ULSI SYSTEMS CO , HITACHI LTD
发明人： NAKAI KIYOSHI , ITO YUTAKA , HASHIMOTO TAKESHI , KATO HIDEAKI
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C29/42 , G11C29/00
摘要： A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

3. 发明专利

JP2004118938A Address counter control system 有权
公开(公告)号：JP2004118938A
公开(公告)日：2004-04-15
申请号：JP2002281045
申请日：2002-09-26
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： INABA TOMOYUKI , NAKAI KIYOSHI , KATO HIDEAKI
IPC分类号： G11C11/403 , G11C8/04
CPC分类号： G11C8/04
摘要： PROBLEM TO BE SOLVED: To realize a reduction in required area and simplification of control in a memory device.
SOLUTION: This system is provided with address counters (AC) 1-0 to 1-12 corresponding to a normal region of data bits as a basis, further, pass switches 2-1, 2-2 are positioned between AC 1-3 and AC 1-9, AC 1-3 and AC 1-4, AC 1-8 and AC 1-9, respectively, for refresh operation of memories. For all bit refresh of a normal region, the pass switch 2-0 is opened, the pass switch 2-1, 2-2 are closed and they are used. As opening and closing of the path switch is switched by finish of operation of the last address of a normal region, specifying addresses continuously can be performed for the AC 1-0 to 1-3 and AC 1-9 to 1-12 in a discontinuous region of a parity bit. The ENd signal is generated by finish of operation of the last address of the discontinuous region, a memory device is shifted automatically to a pause state of low power consumption.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2002025299A DISCRIMINATING METHOD FOR ERROR RATE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002025299A
公开(公告)日：2002-01-25
申请号：JP2000207717
申请日：2000-07-10
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MURANAKA MASAYA , KATO HIDEAKI , ITO YUTAKA
IPC分类号： G11C11/406 , G06F11/10 , G11C7/10 , G11C11/401 , G11C29/08 , G11C29/42 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To provide a discriminating method for an error rate of data having high reliability and a semiconductor integrated circuit device in which power consumption of information holding operation can be reduced while securing high reliability in a memory circuit using a dynamic type memory cell. SOLUTION: This device is started at the time of an information holding mode, reads out plural data held in a dynamic type memory circuit, generates a test bit for correcting erroneous detection, stores it an addition memory circuit, reads out the plural data and test bits corresponding to them with a fixed refresh period by an ECC circuit and performs detection and correction of an error. An error rate selection circuit is provided so that when an error does not exist, a first detecting signal is integrated, and when an error exists, a second detecting signal is integrated so as to have larger weight than the first detecting signal and to reduce the first integration, and that when quantity of the integration exceeds a fixed value, the refresh period is lengthened by the prescribed time and when quantity of the integration becomes smaller than a fixed value, the refresh period is shortened by the prescribed time.

5. 发明专利

JP2000260962A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000260962A
公开(公告)日：2000-09-22
申请号：JP6260499
申请日：1999-03-10
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OYU SHIZUNORI , IWAI HIDETOSHI , ITO YUTAKA , KATO HIDEAKI , SATO KAZUHIKO , OGASAWARA MAKOTO
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To obtain a highly reliable DRAM by improving the refreshing characteristics of the DRAM. SOLUTION: In a semiconductor integrated circuit device, the impurity concentrations in data line-side n- and p-type semiconductor regions 7a and 10a are set relatively higher than those in capacitance element-side n-- and p--type semiconductor regions 7b and 10b. The device is operated by selecting the substrate voltage and data-line voltage, so that the reverse voltage (= data-line voltage + |substrate voltage|) impressed upon a data line-side joining area becomes 2.5 V or smaller. Therefore, the pose characteristic of the device can be improved, while the deterioration of the disturbance characteristic of the device is suppressed.

6. 发明专利

JPH08139082A SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD OF DECIDING END OF FORMATION OF OXIDE FILM, WHICH IS USED FOR THAT DEVICE 失效
公开(公告)号：JPH08139082A
公开(公告)日：1996-05-31
申请号：JP27335094
申请日：1994-11-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASEBE TADAYOSHI , KATO HIDEAKI
IPC分类号： C30B25/16 , H01L21/31
摘要： PURPOSE: To enable a high-accuracy decision of the end of formation of an oxide film without being affected by the temperature in a treating chamber and a variation of an atmosphere by a method wherein infrared rays, which are radiated from a workpiece, are utilized and the decision of the end point of formation of the oxide film is made on the basis of previously inputted film thickness data to show the relation between the film thickness of the oxide film and an infrared intensity. CONSTITUTION: A wafer 2 is transferred in the interior of a treating chamber 1 or to the outside of the chamber 1 by a workpiece transfer mechanism 4. Infrared rays 6 only of a frequency in a prescribed range out of infrared rays 6 radiated from the wafer 2 are transmitted through a filter 7 installed in the vicinity of the wafer 2 and the intensity of the infrared rays 6 transmitted through this filter 7 is measured by an infrared intensity detector 8. An decision of the end point of formation of an oxide film is made by an automatic end point decision means 9 on the basis of previously inputted film thickness data 12 to show the relation between this infrared intensity and the film thickness of the oxide film and after the decision of the end point is made, a power supply of a heating source 3 is turned-off. Moreover, the opening and shutting of a prescribed valve 11 is driven by a process gas control part 10 on the basis of information from the means 9.

7. 发明专利

JPH06267877A HEAT TREATMENT DEVICE 失效
公开(公告)号：JPH06267877A
公开(公告)日：1994-09-22
申请号：JP5353393
申请日：1993-03-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HASEBE TADAYOSHI , KATO HIDEAKI
IPC分类号： H01L21/22 , H01L21/26 , H01L21/31 , H01L21/324
摘要： PURPOSE:To improve the deterioration of temperature recovery at the time of carrying in or out an object to be treated by means of a carrying jig with a simple constitution. CONSTITUTION:In the treatment device which performs necessary treatment by inserting an object 3 to be treated into a heating furnace composed of a quartz tube 2, SiC tube 6, and heater 7 while the object 3 is housed in a carrying jig 4, a heat source 9 is provided for preliminarily heating the carrying jig 4 immediately before the jig 4 is inserted into the heating furnace.

8. 发明专利

JPS5138980A 失效
公开(公告)号：JPS5138980A
公开(公告)日：1976-03-31
申请号：JP11146674
申请日：1974-09-30
申请人： HITACHI LTD
发明人： KATO HIDEAKI , TSUKIKAWA TSUNAO
IPC分类号： H01L21/329 , H01L21/04 , H01L29/06

9. 发明专利

JPH11317505A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11317505A
公开(公告)日：1999-11-16
申请号：JP12314198
申请日：1998-05-06
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NINOMIYA KOICHIRO , MIYATAKE SHINICHI , SUZUKI TSUYUKI , YOKO HIDEYUKI , MIYAUCHI HIDETOSHI , OTA AKIRA , FUJII ISAMU , ITO YUTAKA , KATO HIDEAKI
IPC分类号： G11C11/409 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To avoid the decline in the power supply voltage fed to a column decoder, etc., as well as notably reducing the layout area for power supply wirings. SOLUTION: A pair of power supply lines 5 for supplying a column decoder 4 with power source are formed above the column decoder 4. The power supply lines 5 are connected to other multiple power supply lines 6 comprising power supply lines 6a for supplying a power source voltage VDD as well as ground wirings 6b for supplying a ground potential VSS. The power supply lines 6 formed of wirings between column selecting lines above a memory array 2 is able notably to decrease the decline in the power supply voltage fed to the column decoder 4, by dispersing the power supply using multiple power supply lines 6. Furthermore, since the power supply is dispersed by the power supply lines 6, the wiring width of the power supply lines 5 can be made narrow.

10. 发明专利

JPS6234155B2 失效
公开(公告)号：JPS6234155B2
公开(公告)日：1987-07-24
申请号：JP1574181
申请日：1981-02-06
申请人： HITACHI LTD
发明人： YOSHIDA ISAO , OKABE TAKEAKI , KATSUEDA MINEO , NAGATA MINORU , MATSUZAWA MANABU , ITO HIDESHI , ASHIKAWA KAZUTOSHI , KATO HIDEAKI , ITO MITSUO
IPC分类号： H03F1/52 , H01L27/02 , H01L27/06 , H01L29/06 , H01L29/78 , H02H7/20 , H03F1/00 , H03F1/42

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