会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明专利
    • CONTROL DEVICE FOR GATE
    • JPS63178757A
    • 1988-07-22
    • JP600987
    • 1987-01-16
    • HITACHI LTD
    • KASHIWAZAKI HIROSHIKANO TAKASHI
    • H02M1/088
    • PURPOSE:To secure the conduction of a thyristor arm, by outputting a reignition pulse after a set time from outputting a normal gate pulse. CONSTITUTION:A forward voltage, applied on (n) sets of thyristors S1-Sn, constituting the arm of a thyristor converter and connected in series, is detected by a detector FV whereby ignition is driven from a pulse amplifier PA through a pulse transformer PT. This control circuit is equipped with a controller CC and outputs an ON pulse P1 as well as an OFF pulse P2 to a flip-flop (FF) circuit. Further, the control circuit is equipped with an AND circuit AN, a differential circuit DF and a time delay circuit T1. According to this constitution, the output of the time delay circuit T1 is eliminated after a time T1 even when the output of the detector FV has been left in being outputted, therefore, the outputs of the AND circuits AN1, AN may be eliminated once. An output is generated in the differential circuit DF when the output is generated again after a time T2 whereby the thyristors S1-Sn are supplied with gate pulses.
    • 8. 发明专利
    • CALCULATION SYSTEM FOR SHORTEST ROUTE
    • JPS62168267A
    • 1987-07-24
    • JP20652885
    • 1985-09-20
    • HITACHI LTDHITACHI SEIBU SOFTWARE KK
    • SUZUKI MICHIOKANO TAKASHIHOSHI TORUKASHIO JIRO
    • G06F17/10
    • PURPOSE:To improve the processing efficiency for calculation of the shortest route by treating adjacent matrices where the relation between adjacent nodes is shown by the elements of '1' and '0' by means of logical operation of bits. CONSTITUTION:In a network consisting of nodes A-F, each element of an adjacent matrix ¦A¦ containing an element of '0' or '1' showing an adjacent state between two nodes is set at a single bit. Then the rows of the ¦A¦ are stored in the memory areas (1)-(6) with the columns stored in the memory areas (7)-(12) respectively. While areas (13)-(24) are set for arrivable matrices ¦R1¦-¦Rn¦ expressed by ¦Rn¦=¦Rn-1¦*¦A¦. The calculation of the arrivable matrix R2 is calculated by performing an operation for an AND corresponding to the bits of the 1st row (13) of the arrivable matrix ¦R1¦ (=¦A¦) and the 1st col umn (7) of an adjacent matrix ¦A¦ and then setting the arithmetic result at '1' since the contents of said register are not equal to '0'. A distance matrix is calculated by an equation based on the arithmetic result of the arrivable matrix. Thus is it possible to calculate the shortest route with small memory capacity and high arithmetic efficiency.
    • 9. 发明专利
    • PACKET SWITCHING EQUIPMENT
    • JPS62115949A
    • 1987-05-27
    • JP25386985
    • 1985-11-14
    • HITACHI LTDHITACHI SEIBU SOFTWARE KK
    • SUZUKI MICHIOKANO TAKASHIHOSHI TORUKASHIO JIRO
    • PURPOSE:To improve the processing ability by making a packet switching circuit into the self-rooting switching circuit composed of plural switching elements mutually connected to the line interface and executing the necessary switching control in accordance with the transfer packet from the line interface by the control part. CONSTITUTION:Line interfaces 4-6 provided corresponding to respective lines examine the classification of the received packet, discriminates the packet which may be conveyed to the address line as it does and the packet to need the processing by a control part 2, the former sticks the address of the conveying destination line interface, sends it to a self-rooting packet switching circuit 3 and the latter transfers it to the control part. The self-rooting packet switching circuit 3 sends the sent packet to the equivalent line interface in accordance with the address stuck to it. Thus, the burden of the control part is decreased, further, the problems of the competition and the congestion of the access to the common memory will not occur and the wide improvement of the processing ability of the packet switching equipment can be expected.