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1. 发明专利

JPS5633743A INFORMATION PROCESSOR 失效
公开(公告)号：JPS5633743A
公开(公告)日：1981-04-04
申请号：JP10948279
申请日：1979-08-28
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： G06F11/34 , G06F11/22
摘要： PURPOSE:To increase the reliability of the fault data, by storing the data of full ''0'' and full ''1'' in the adjacent areas after the fault data in case the fault data is shunted to the memory and then referring to the three results. CONSTITUTION:Both the set/reset decoder 12 and the set/reset controller 11 are provided between the control memory control part 4 and the error register 10. Then the instruction to turn the faulty register into the full ''0'' plus the instruction to turn the register into the full ''1'' are set to the part 4 as the data shunting microorder. Thus the fault data plus the ''0'' and ''1'' data are referred to in case the fault data is shunted to the memory device 1 via the error register 10, the OR gate, latches 7 and 8, the arithmetic part 9 and the memory register 6 each. In such way, the reliability can be increased for the faulty data.

2. 发明专利

JPS53140014A MAGNETIC DISC CONTROLLER 失效
公开(公告)号：JPS53140014A
公开(公告)日：1978-12-06
申请号：JP5429277
申请日：1977-05-13
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： G11B27/10 , G06F3/06 , G11B5/09 , G11B5/55 , G11B20/10 , G11B21/08
摘要： PURPOSE:To reduce the rotation awaiting time of a disc as long as the transfer unit of data is one track unit by providing means for the length of the data and means for accommodation so as to accomplish the access through the rotation awaiting operation of the disc.

3. 发明专利

JPS6338318B2 失效
公开(公告)号：JPS6338318B2
公开(公告)日：1988-07-29
申请号：JP16978480
申请日：1980-12-02
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： B41J29/46 , B41J5/30 , B41J25/20 , G06F3/12 , G06K15/00

4. 发明专利

JPS60140451A MEMORY BUS SYSTEM 失效
公开(公告)号：JPS60140451A
公开(公告)日：1985-07-25
申请号：JP24549283
申请日：1983-12-28
申请人： HITACHI LTD
发明人： TAGUCHI KAZUYOSHI , INAO HIROTOSHI , ABE AKIRA
IPC分类号： G06F15/16 , G06F13/16 , G06F13/18
摘要： PURPOSE:To improve the performance of the entire titled system by storing an address and a data from a processor to a memory buffer, and releasing the common bus before the start of a memory operation to improve the utilizing efficiency of a common bus. CONSTITUTION:The processor receiving a reception signal 13 transmits an address to a common address bus 5. If it is a write request, a write data is outputted to a common data bus 4 at the same time, a write command is transmitted to a command line 16. These commands are fed to a bus control section 11 to inhibit the succeeding reception signal (13) transmission. The command controls a buffer control section 10 that the data and address on the common buses 4, 5 are fetched in a register of a memory buffer 6 in the clock timing 15.

5. 发明专利

JPS5447446A MAGNETIC DISC CONTROL UNIT 失效
公开(公告)号：JPS5447446A
公开(公告)日：1979-04-14
申请号：JP11268077
申请日：1977-09-21
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： G11B27/10 , G06F3/06 , G11B5/09
摘要： PURPOSE:To reduce the waiting state for the disc rotation only in case the data transfer is based on a single track unit, by dividing one track of the disc into plural numbers of the access unit. CONSTITUTION:When the access of the disc is based on a single track unit, one track of the disc is divided into access units 2 (access units 1 collected in the same number of units) which can perform an independent access for writing. Disc control unit 10 comprises control circuit 4, address generator circuit 5, address register 6 within memory buffer area, memory address register 7, adder circuit 8, FF9 to indicate data length 1-track amount and access unit 2 number memory 11 respectively. Circuit 4 is connected to processor 1, disc unit 3, memory 2 and others, and receives the read/write indication from unit 1, the number of access unit 1 to start access, the information of the byte number to be transferred and others to then set the memory address performing storage and reading of the data to register 7 and 6. Thus, unit 3 is given an access.

6. 发明专利

JPS5360524A BUFFER CONTROL SYSTEM 失效
公开(公告)号：JPS5360524A
公开(公告)日：1978-05-31
申请号：JP13531076
申请日：1976-11-12
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： G06F13/12 , G06F3/00 , G06F3/06 , G06F13/00
摘要： PURPOSE:By means of the state in use of the data buffer equipped to a peripheral equipment and the interface of a memory control circuit, the transmission of an access signal from the peripheral equipment is controlled, thereby achieving the efficient buffer control.

7. 发明专利

JPS63209867A PRINTER CONTROL DEVICE 失效
公开(公告)号：JPS63209867A
公开(公告)日：1988-08-31
申请号：JP4256387
申请日：1987-02-27
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： B41J25/20 , G06K15/12 , H04N1/00 , H04N1/04 , H04N1/32
摘要： PURPOSE:To obtain identification information on interface impediment due to timing shaft delay between a printer and a controller by printing a counter mark outside a printing area when the end of a page is detected. CONSTITUTION:If a page end generation decoder 5 detects a page end, a page end signal 11 is generated. Simultaneously, a counter mark 15 is printed by a counter mark printing circuit 7. When the timing shafts of a printer and a controller match to each other, the counter mark 15 is printed at the rear end of a useable printing area 14. If any distrubance generates in the timing shaft of the controller, the counter mark is printed at a position which is not relevant to the rear end of the effective printing area. When the above method is used, the impediment of an interface can be traced back to its source, whether to the printer or to the controller, for identification when such an impediment generates, thus saving time for remedy.

8. 发明专利

JPS6356476A PRINTER CONTROLLER 失效
公开(公告)号：JPS6356476A
公开(公告)日：1988-03-11
申请号：JP19881586
申请日：1986-08-27
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： G06K15/12 , B41J2/485 , B41J25/20 , G06F3/12
摘要： PURPOSE:To obtain a printer controller capable of printing a printing paper with a mark which can be discriminated from sideways when the printed papers are stacked, by developing a side mark into dots on a side mark dot memory, synthesizing the mark in a full-dot memory, and printing the mark. CONSTITUTION:A main processing circuit 4 edits one page in a page buffer 5, and gives a dot development command to a printing processing circuit 6 through a printing data development command line 14. When the development of one page is completed, the circuit 4 sets a side mark resistor counter 10 at an initial stage, and gives a command for synthesis of a side mark to the circuit 6 through a side mark synthesis command line 13 on a page basis. On receiving the side mark synthesis command, the printing processing circuit 6 reads from rasters in a side mark dot memory 1 designated by the side mark raster counter 10, and develops the same raster N-times at an upper part and both side parts of a full-dot memory 7. By this, the content of a list can be indicated at the side of the list simultaneously with outputting the list.

9. 发明专利

JPS58214978A Page editing system 失效
标题翻译：页面编辑系统
公开(公告)号：JPS58214978A
公开(公告)日：1983-12-14
申请号：JP9765182
申请日：1982-06-09
申请人： Hitachi Ltd
发明人： INAO HIROTOSHI
IPC分类号： G06F3/12 , B41J21/00 , G06K15/00
CPC分类号： G06K15/00
摘要： PURPOSE:To increase the layout processing speed and to decrease the editing time, by reading a master data out of a mask memory when necessary in the data conveying routine of each class and therefore deleting the mask production processing step from a raster data transfer routine of a high traveling frequency. CONSTITUTION:A main control circuit 4 of a printer controller 2 obtains the character pattern addresses corresponding to the character codes equivalent to a page from a central processor 1. Then the circuit 4 delivers a layout parameter to a character layout circuit 5 for each character, and the circuit 5 gives the layout parameter to a mask production control circuit 9 to produce a mask data. This mask data is stored in a mask memory 10. Then the memory 10 is read out by a mask processing control circuit 11 to perform the mask processing when the bit address processing is carried out for layout of both the first and last words of each raster.
摘要翻译：目的：为了增加布局处理速度并减少编辑时间，通过在每个类的数据传送例程中必要时从掩模存储器读取主数据，并且因此从光栅数据传送程序中删除掩模生成处理步骤行驶频率高。构成：打印机控制器2的主控制电路4获得与来自中央处理器1的页面相当的字符代码对应的字符图案地址。然后，电路4将布局参数传送给每个字符的字符布局电路5，并且电路5给掩模生产控制电路9给出布局参数以产生掩模数据。该掩模数据被存储在掩模存储器10中。然后，当执行位地址处理以对每个栅格的第一个和最后一个字的布局进行位地址处理时，由掩模处理控制电路11读出存储器10以执行掩码处理。

10. 发明专利

JPS553053A INTERRUPTION CONTROL CIRCUIT 失效
公开(公告)号：JPS553053A
公开(公告)日：1980-01-10
申请号：JP7536778
申请日：1978-06-23
申请人： HITACHI LTD
发明人： INAO HIROTOSHI
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To eliminate the erroneous control for the interruption control circuit which conveys the state change of the lower-rank unit to the upper-rank unit in the form of the interruption, by sampling the state of the lower-rank unit via the reading indication of the upper-rank unit and thus reading out the latest state. CONSTITUTION:The state of lower-rank unit 1 varies, and thus interruption control circuit 2 gives the interruption request to upper-rank unit 3 via differential circuit 4 and interruption request flip-flop 5. Receiving the interruption request, unit 3 samples and reads the state of unit 1 from lower-rank unit state line 8 and via reading indication line 11. Thus, the latest state of the lower-rank unit can be known, accordingly eliminating the erroneous control in comparison with the reading by holding the old state.

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