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1. 发明专利

JPH0758766A CONSTITUTION CONTROL SYSTEM FOR LOOP TYPE NETWORK 失效
公开(公告)号：JPH0758766A
公开(公告)日：1995-03-03
申请号：JP20632393
申请日：1993-08-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUMOTO AKIYUKI , HONDA AKINORI , YOKOTA NAGANARI , KISHIMOTO HIDEO
IPC分类号： H04L12/437
摘要： PURPOSE:To provide a constitution control system in which an operation can be continued without setting a loop back at the time of the fault only of a preliminary system, in a bidirectionary double loop type network. CONSTITUTION:A node 1a which detects the fault of the present system sets a loop back 8 from the preliminary system to the present system, and transmits a first control signal 6 indicating that the physical circulation of the present system is impossible, and a second control signal 7 indicating the node number of the node 1a through transmission lines 2b, 2c, and 2d of the present system. A node 1d which detects the fault of the preliminary system, and receives the second signal according to the setting of the loop back 8, sets a loop back 9 from the present system to the preliminary system. Thus, at the time of the fault only of the preliminary system, the operation can be continued by the present system without operating fault processing by the loop back.

2. 发明专利

JPH06236299A METHOD AND DEVICE FOR MONITORING SYSTEM 失效
公开(公告)号：JPH06236299A
公开(公告)日：1994-08-23
申请号：JP2221993
申请日：1993-02-10
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MAEJIMA YUKITO , HONDA AKINORI , YAMAZAKI MOTOAKI , TAKANO MAKOTO , SAITO ISAO
IPC分类号： G06F11/30
摘要： PURPOSE:To surely collect information by monitoring a slave processor system fault by a main processor system in the processor system of master/slave relation. CONSTITUTION:This device is provided with a means for periodical inquiry from a main processor 10 to a slave processor 20, system monitor timer means 24 for monitoring the infinite loop of the slave processor 20, means for interrupting (25) the slave processor when the system monitor timer overflows, collecting program information under execution, after storing the pertinent information in a memory area 21, interrupting communication with the main processor 10, means for detecting the fault of the slave processor 20 when the response of the inquiry to the specific slave processor 20 is not returned at the main processor 10 for a certain period of time, means for resetting (26) the pertinent slave processor 20 from the main, processor 10, and means for reading the program information stored by the pertinent slave processor 20 from the main processor 10.

3. 发明专利

JP2003143236A GATEWAY 审中-公开
公开(公告)号：JP2003143236A
公开(公告)日：2003-05-16
申请号：JP2001332775
申请日：2001-10-30
申请人： HITACHI LTD
发明人： NODA MITSUHIRO , MATSUI SUSUMU , HONDA AKINORI
IPC分类号： H04L12/66
摘要： PROBLEM TO BE SOLVED: To provide a LAC (L2TP ACCESS Concentrator) use gateway that can relieve Web traffic in an access network of an ISP selection type IP network. SOLUTION: The gateway 104 connected to the access network 105 containing a plurality of ISP networks 108 and provided with a LAC function that transfers a PPP frame received from a user terminal to the ISP networks via an L2TP connection set onto the access network, includes: a cache server interface 112 to be connected to a Web cache server; and packet transfer controllers (81A to 81C, 87) that select the PPP frame including a request message of Web contents in its payload part among a PPP frame stream received from the user terminal and transfer the request message denoted by the PPP frame to the cache server via a cache server interface.

4. 发明专利

JPH09307566A TRAFFIC SHAPING DEVICE 失效
公开(公告)号：JPH09307566A
公开(公告)日：1997-11-28
申请号：JP12345096
申请日：1996-05-17
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： AKITA TSUYOSHI , HONDA AKINORI , IRIBE SHINICHI , YANASE KIYOSHI , NAKAMURA MASAHIKO , SATO TETSUYA , MORITANI HIROSHI , YOKOTA NAGANARI
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/807 , H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To provide a traffic shaping device by reducing an external device such as a memory and selecting a cell requiring a fastest transmission time as a cell to be sent next. SOLUTION: In the case that a cell reaches a free queue or one cell is sent from a transmission control section 14, a transmission schedule time of a head cell of a queue of a connection to which the arrived cell or a transmitted cell belongs is calculated by a transmission schedule time arithmetic section 12. A sorting section 13 conducts processing by using an obtained transmission schedule time to decide a cell to be sent fastest among cells in a cell buffer section 11 and its transmission schedule time. When the transmission schedule time of the transmission scheduled cell decided by the sorting section 13 comes and the transmission control section 14 does not receive a cell transmission suppression signal, the control section 14 extracts the corresponding cell from the cell buffer suction 11 and sends the cell and reparts it to a transmission schedule time arithmetic section 12 calculating the transmission schedule time of a succeeding cell.

5. 发明专利

JPS57209547A COLLECTING DEVICE FOR PROGRAM EXECUTING CARRIER INFORMATION 失效
公开(公告)号：JPS57209547A
公开(公告)日：1982-12-22
申请号：JP9385081
申请日：1981-06-19
申请人： HITACHI LTD
发明人： HONDA AKINORI
IPC分类号： G06F11/28 , G06F9/38 , G06F11/36
摘要： PURPOSE:To collect a correct branch instruction address, by discriminating types of past instructions stored, when an instruction reading address is not consecutive to an instruction reading address just before and a branch instruction is detected. CONSTITUTION:Registers 1-6 always stores an instruction address and an instruction while transferring them in order. An output of an instruction address storage register being an instruction reading address just before added by (1) to the output of an addition circuit 12 and the instruction reading address at present are compared at an exclusive OR circuit 13. Decoders 7 and 8 decode the content of instruction storage registers 5 and 6, specific branch instruction patterns are detected, and the content of instruction address storage registers 2 and 3 representing a correct branch instruction address through AND circuits 9 and 10, an OR circuit 11 and an AND circuit 15 is selected according to the detection of the branch instruction pattern and is outputted to a branch instruction exeucting address output line 26 for collection.

6. 发明专利

JP2003283577A COMMUNICATION DEVICE PROVIDED WITH IPv4/IPv6 DUAL STACK FUNCTION 有权
标题翻译：具有IPv4 / IPv6双栈功能的通信设备
公开(公告)号：JP2003283577A
公开(公告)日：2003-10-03
申请号：JP2002077492
申请日：2002-03-20
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TACHIKAWA ATSUSHI , HONDA AKINORI , NAKAZAWA HIROAKI , MATSUKI JOSUKE
IPC分类号： H04L12/66 , H04L12/701 , H04L12/781 , H04L12/903
摘要： PROBLEM TO BE SOLVED: To provide an access server for connecting an access network and an access server for dealing with Internet Protocol Version 4 (IPv4) or an IPv4 network or an IPv6 network at low line cost by utilizing the existent IPv4 network. SOLUTION: In an access server 103 for dealing with IPv4/IPv6 for interconnecting an access network 101 to which a plurality of user terminals 100 are connected and an access server 104-1 for dealing with IPv4 or an IPv4 network 105-2 or an IPv6 network 106, the access server has a control means for transferring a Point-to-Point Protocol (PPP) packet received from a user terminal 100 to the access server 104-1 for dealing with IPv4 or for extracting an IP packet from said PPP packet based upon the contents of said PPP packet and the contents of a table 402 or 403 registered in advance, and for transferring the extracted IP packet to the IPv4 network 105-2 or the IPv6 network 106. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种接入服务器，用于通过利用现有的IPv4网络以低线路成本连接用于处理因特网协议版本4（IPv4）或IPv4网络或IPv6网络的接入网络和接入服务器。解决方案：在用于处理用于互连多个用户终端100连接的接入网络101的IPv4 / IPv6的接入服务器103和用于处理IPv4或IPv4网络105-2的接入服务器104-1 或IPv6网络106，所述接入服务器具有控制装置，用于将从用户终端100接收到的点对点协议（PPP）分组传送到接入服务器104-1以处理IPv4或者从所述PPP分组基于所述PPP分组的内容和预先登记的表402或403的内容，并且用于将所提取的IP分组传送到IPv4网络105-2或IPv6网络106.权利要求（ C）2004，JPO

7. 发明专利

JPH08107419A INITIAL PROGRAM SETTING METHOD FOR ATM EXCHANGE 失效
公开(公告)号：JPH08107419A
公开(公告)日：1996-04-23
申请号：JP24266194
申请日：1994-10-06
申请人： NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , TOSHIBA CORP
发明人： TAKANO MAKOTO , ONO HIROYASU , SAITO ISAO , MAEJIMA YUKITO , HONDA AKINORI , TSUMURA TOKUMITSU , NUNOKAWA TADATOU , IKEDA TAKASHI , MAENO JUNICHI
IPC分类号： G06F9/445 , G06F13/00 , H04L12/28 , H04Q3/00
摘要： PURPOSE: To provide an initial program setting method for ATM exchange with which the programs of different versions can be automatically loaded from a file to a main storage device corresponding to the number of times of initial setting processing start and the down load of the program can be requested from a control node to a managing node at the time of the file update. CONSTITUTION: A control node 2 counts the number of times of initial setting processing start at this control node 2 while using a counter 22a and decides the program stored in a program file 23 to be loaded to a main storage device 21 based on this result and the program is loaded to the main storage device 21 and activated. Besides, when there is no program to be loaded in the program file 23 or the update of the file is instructed, the down load request of the program is automatically transmitted from the control node 2 to a managing node 1 and the program is down loaded from the managing node 1.

8. 发明专利

JPH06268674A PATH SETTING SYSTEM 失效
公开(公告)号：JPH06268674A
公开(公告)日：1994-09-22
申请号：JP5614293
申请日：1993-03-16
申请人： NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , TOSHIBA CORP
发明人： TAKANO MAKOTO , MATSUO NAOKI , TSUMURA TOKUMITSU , MAEJIMA YUKITO , HONDA AKINORI , MATSUDA MINORU , OCHIAI TAMIYA , MAENO JUNICHI
IPC分类号： H04M3/00 , H04L12/48
摘要： PURPOSE:To provide a path setting system capable of decreasing the processing of a switch node while reducing the number of required signals and eliminating necessity for recording all the via nodes in a signal for setting. CONSTITUTION:A control node 200 and switch nodes 201, 202 and 203 set adjacent paths on an ATM speech path between mutually adjacent nodes. Afterwarcs, the switch nodes 201, 202 and 203 repeatedly transmit a direct path setting request signal to the adjacent node so as to request the setting of a direct path. When the already set direct path is provided between the control node 200 and the switch node receiving the direct path setting request signal the relevant switch node repeates the direct path setting request signal through this already set direct path to the control node, and in the other case, this direct path setting request signal is abandoned. Then, the control node transmits the information on a new direct path by using this set path.

9. 发明专利

JPH03258196A TIME SWITCH 失效
公开(公告)号：JPH03258196A
公开(公告)日：1991-11-18
申请号：JP5742290
申请日：1990-03-08
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HONDA AKINORI , OWADA KENICHI
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To warrant a TSSI with simple control by controlling a delay time so as to be increased by one as to a less delay time among time slots forming a relevant channel. CONSTITUTION:A single buffer memory switch 1 uses odd number highways 3, 5,...11, 13 for input output highways and uses even number highways 2, 4,...10, 12 for feedback highways. There is a relation in this system that data on a younger input slot is outputted to an output time slot of a younger number and as to time slots of a same channel, mixture of delay times 0 and 2 is not caused and the difference between delay times at most 1. Thus, as to time slots with less delay times forming the channel, the switching is controlled so as to increase the delay time by one via the feedback highways. Thus, the TSSI is warranted.

10. 发明专利

JPH0388534A PACKET SWITCHING SYSTEM 失效
公开(公告)号：JPH0388534A
公开(公告)日：1991-04-12
申请号：JP22303889
申请日：1989-08-31
申请人： HITACHI LTD
发明人： MOTOKI YOSHIKO , HONDA AKINORI , MORITA TAKASHI
IPC分类号： H04L12/02 , H04L12/70 , H04Q3/62 , H04Q11/04
摘要： PURPOSE:To eliminate the need for hardware for packet switching, a high-speed transmission line for packet transmission, and a highspeed transmission for a communication among decentralized processors by referring to a switching table for an extension ISDN terminal-private exchange logical channel and a private exchangeISDN network channel which is provided in a line interface device. CONSTITUTION:When a line interface control part 23 receives a packet for control regarding a termination request from an ISDN network over a D channel, a system control part 32 searches for TEI and a line number as to an ISDN terminal to terminate according to its incoming address and informs the line interface control part 23 of the retrieval results and the line interface control part 23 searches for a free logical channel on its physical line. As for the TEI, logical channel, and line number for the termination-side ISDN terminal, the line interface control part 23 generates a table of network-side origination with a CR packet received from an ISDN network 6 and then a system control part 32 makes a search according to the incoming address.

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