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1. 发明专利

JPH04205158A DATA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPH04205158A
公开(公告)日：1992-07-27
申请号：JP32884790
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： HIRAHATA KENJI , YANAGIDA TOMOHIKO , KASUGA HIDEO , KOBAYASHI MASATAKA , KONDO NOBUKAZU , IDO AKIRA , KAWASHIMA HIDEYUKI
IPC分类号： G06F13/28
摘要： PURPOSE:To simplify hardware by adding transfer information as a command to transfer data, transferring the data according to it, and enabling the transfer of the data without considering the number of bytes. CONSTITUTION:When 10 data is written in a main storage by DMA, the IO data are inputted to a system bus interface part 16 through a system bus 20 and divided into data and commands. The data are inputted to a data buffer 15 and the commands are inputted to a command decoder 18. The decision result of the command decoder 18 is inputted to a DMA control part 17, which sends a signal to a processor interface part 14 so as to output the data from the data buffer 15 to a processor bus 12 according to the decision result. When final data is sent, the data is outputted to a processor bus 14 and the software is informed of the end of the DMA.

2. 发明专利

JPH04186458A DMA CONTROL SYSTEM 失效
公开(公告)号：JPH04186458A
公开(公告)日：1992-07-03
申请号：JP31393090
申请日：1990-11-21
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： YANAGIDA TOMOHIKO , KONDO NOBUKAZU , KAWASHIMA HIDEYUKI , HIRAHATA KENJI , MATSUDA TOSHIHIKO , HARUTA HIDEO , KOBAYASHI MASATAKA , IDO AKIRA
IPC分类号： G06F13/28
摘要： PURPOSE:To speed up DAM by allowing a DMA control device to open a local bus to an I/O after being turned to the master device of a processor bus when the I/O on the local bus is to execute DMA to a memory on the processor bus. CONSTITUTION:When the I/O 4 on the local bus 5 requests DMA, the DMA control device 6 is turned to the master of the processor bus 3, and when the DMA requested by the I/O 4 is memory read, enters data corresponding to the bus width of the bus 3 in accordance with the bus cycle of the bus 3 and then is turned to the slave state of the bus 3. At the time of inputting data from a memory, the device 6 permits the I/O 4 to executes DMA and sends data to the I/O 4 to complete the DMA. When the DMA requested by the I/O 4 is memory write, the device 6 is instantaneously turned to the slave state of the bus 3, permits the I/O 4 to execute DMA, inputs data sent from the I/O 4. When the data sending of the I/O 4 is completed, the device 6 is turned to the master of the bus 3 and writes data in the memory to complete the DMA. Thus DMA can rapidly be executed.

3. 发明专利

JPH05197675A SYSTEM FOR ARBITRATING BUS RIGHT 失效
公开(公告)号：JPH05197675A
公开(公告)日：1993-08-06
申请号：JP979492
申请日：1992-01-23
申请人： HITACHI LTD
发明人： WATABE KEN , ONISHI KATSUYOSHI , FUJIGAMI YOSHIHIRO , HIRAHATA KENJI
IPC分类号： G06F13/362
摘要： PURPOSE:To permit a second data transfer controller to transfer data by taking back the bus right without waiting for the release of a bus in the case the request of the bus right is generated inside the second data transfer controller after the bus right is given to the first data transfer controller. CONSTITUTION:A flag (b) under use of a bus by monitoring three signals of bus request(BR), bus grant(BG), and bus grant acknowledge (BGACK) signals and a data transfer control signal is used for arbitrating the bus right. The BG signal is equipped with a function indicating the start of the bus right arbitration processing and a function requesting a peripheral device being the bus master to make the bus right arbitration device return the bus right.

4. 发明专利

JPH05189370A MULTIPORT MEMORY 失效
公开(公告)号：JPH05189370A
公开(公告)日：1993-07-30
申请号：JP366692
申请日：1992-01-13
申请人： HITACHI LTD
发明人： FUJIGAMI YOSHIHIRO , IKEDA NAOYA , ONISHI KATSUYOSHI , WATABE KEN , HIRAHATA KENJI
IPC分类号： G06F13/38 , G11C11/401 , G11C11/41
摘要： PURPOSE:To unnecessitate the installation of the recognition means of the pointer position of a serial access memory (SAM) to the outside and to move a pointer in high speed by providing a means automatically serial-data- transferring inside without giving an instruction from outside. CONSTITUTION:When a transfer control 109 is started from the outside, the pointer in a SAM part 1 is necessary to be always stored/monitored. Then, in order to automatically transfer data, a pointer check 111 is provided, At the time of detecting that the poiner reaches the last of the SAM part 105, a poiner check 111 starts the transfer control 109 through the use of a low address storage means and the address value of an incrementer 110. In order to set which of data transfer of two kinds, which are serial read data transfer or serial write data transfer, to execute, a R/W signal is provided for transfer control 109 to decide which to execute serial read data transfer or serial write data transfer.

5. 发明专利

JPH07219889A DATA TRANSFER METHOD 失效
公开(公告)号：JPH07219889A
公开(公告)日：1995-08-18
申请号：JP1080994
申请日：1994-02-02
申请人： HITACHI LTD
发明人： SAWADA SUNAO , HIRAHATA KENJI , WATABE KEN , SATO HIROSHI
IPC分类号： G06F13/28 , G06F13/00
摘要： PURPOSE:To provide a data transfer method which enables data transfer to an discontinuous address without re-setting the address by a data output device. CONSTITUTION:When transfer data 22 is written in a data buffer 2, the data output device 6 simultaneously writes an attribute value 12 indicating the kind of transfer data 11. A DMA controller 8 decides the address of a memory where transfer data 11 is stored based on the attribute value Thus, it is not required that the data output device re-sets the address in the DMA controller in data transfer so that data is continuously transferred.

6. 发明专利

JPH06244839A COMMUNICATION DEVICE 失效
公开(公告)号：JPH06244839A
公开(公告)日：1994-09-02
申请号：JP2644793
申请日：1993-02-16
申请人： HITACHI LTD
发明人： HIRAHATA KENJI , WATABE KEN , SAWADA SUNAO
IPC分类号： H04L12/28
摘要： PURPOSE:To obtain the router corresponding to plural ports by providing a means discriminating which port data comes from, detecting a header element from block data and reconstituting header parts for every port. CONSTITUTION:As a communication control part outputs also channel signals 511 to 514 successively when the part receives data from a LAN side and outputs these successively, the header detection circuits corresponding to channel signals 511 to 514 of header detection circuits 41a to 41d provided within a high speeding means operate and output headers to each of headers FIFO 44a to 44d. Thus, the high speeding means which receives the data from different transmission origins discriminates coexisting data and reconstitutes each header. As a result, high speed with the use of the head in the routing in a middle and low speed LAN can be performed because plural ports are fetched in the internal FIFO 44a to 44d without making the packet header coexist from the plural ports even if the plural ports are connected with a device connecting networks mutually.

7. 发明专利

JPH0583270A NETWORK SYSTEM AND CONTROL PROGRAM TRANSFER SYSTEM 失效
公开(公告)号：JPH0583270A
公开(公告)日：1993-04-02
申请号：JP24182591
申请日：1991-09-20
申请人： HITACHI LTD
发明人： WATABE KEN , ONISHI KATSUYOSHI , HIRAHATA KENJI , OGURA TOSHIHIKO , IKEDA NAOYA , ENOMOTO HIROMICHI
IPC分类号： H04L12/42
摘要： PURPOSE:To eliminate the need of providing an external storage device in a device connected to a trunk line ring and to miniaturize the housing of the device by loading a control program in accordance with a prescribed method from other device through a network. CONSTITUTION:As for a concentrating/wiring device 1, communication controllers 21-23, and stations 31-3n for constituting a node, even if they are connected physically, they are not always connected logically. Also, MAC(media access control) layer control means 41, 421-423, and 431-43n control transmission and reception in accordance with a control program. In such a state, at the time of transferring a control program to other node, the node detaches the connection to the node which does not execute a transfer, executes one-to-one connection to the node of a transfer destination and transfers the control program. After the transfer, the connection is finished, the control program is started and released from the detachment, and by a control program transfer system joined to the network, the control program is transferred. In such a way, the device housing can be miniaturized.

8. 发明专利

JPH04195190A ADDRESS CONVERTER FOR DISPLAY MEMORY 失效
公开(公告)号：JPH04195190A
公开(公告)日：1992-07-15
申请号：JP33156190
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： SUKAI KAZUO , IDO AKIRA , KONDO NOBUKAZU , KOBAYASHI MASATAKA , MATSUDA TOSHIHIKO , HARUTA HIDEO , YANAGIDA TOMOHIKO , HIRAHATA KENJI , KAWASHIMA HIDEYUKI
IPC分类号： G06F12/02 , G09G5/00 , G09G5/36 , G09G5/39
摘要： PURPOSE:To allow the formation of a transfer address with a small-scale logic circuit even if different displays are connected by storing the kinds of address conversion and converting the logic address of display data to a physical address according to the stored kinds. CONSTITUTION:A memory means 41 which stores the kinds of the address conversion and an address converting means 43 which converts the logic address of the display data to one or >=2 physical addresses according to the stored kinds are provided. The bits having a processor address signal 51 and transfer address signal 53 constituting the conversion address 60 which is the address before the conversion are alternated according to mode information 59 in a register section 41. The same control of the formation of the transfer address is executed in terms of hardware as well regardless of modes even if the display of different display area sizes and display modes are connected.

9. 发明专利

JPH07221797A FIFO MEMORY SYSTEM 失效
公开(公告)号：JPH07221797A
公开(公告)日：1995-08-18
申请号：JP1147494
申请日：1994-02-03
申请人： HITACHI LTD
发明人： WATABE KEN , HIRAHATA KENJI , SAWADA SUNAO , SATO HIROSHI
IPC分类号： G06F5/06 , G11C7/00 , H04L12/66 , H04L13/08
摘要： PURPOSE:To utilize effectively a memory resource even when the frequency of data transfer per channel differs by revising setting of number of divisions of FIFO depending on the frequency of occurrence of data written in the FIFO and number of channels. CONSTITUTION:In the case of CSMA/CD compatible system, when header data received from a network whose channel is 0 are stored in the FIFO, a write channel select signal is used to select a write counter 82 or channel 0 and the count is used for low-order 4-bits of a write address. Furthermore, the write channel select signal is used as it is for high-order 2-bits of the write address. When header data for channels 1-3 are written, the select signal and a write counter 82 for each channel are combined similarly to be the write address and it is given to a RAM. When data of each channel are read, a read channel select signal and a read counter 82 for each channel are combined similarly as a read address, and it is given to the RAM.

10. 发明专利

JPH0750666A ROUTING SYSTEM 失效
公开(公告)号：JPH0750666A
公开(公告)日：1995-02-21
申请号：JP19446593
申请日：1993-08-05
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： HIRAHATA KENJI , WATABE KEN , SAWADA SUNAO , SATO HIROSHI , SASAKI MASAHITO
IPC分类号： H04L12/00
摘要： PURPOSE:To attain the high speed routing of packet data by providing a load distributing means having a queue for storing a processed result in a routing processor in a communication equipment in which networks are mutually con nected. CONSTITUTION:Modules on an LAN connected with a communication control part 5a are connection-controlled, and routing for operating a packet processing is operated by a routing processor 3. This processor 3 is equipped with a load distributing means 4, and the means 4 is equipped with the queue for storing the processed result in a packet buffer 33 corresponding to the ports of the communication control part 5a or the like, and a data sequence number ID from the control part 5a is fetched. Then, each header is reconstituted from data coexistingly inputted from the plural ports, the ID is added to each packet, and the routing of the established routing information in the packet in the buffer 3 is operated at a high speed.

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