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1. 发明公开

EP0511484A2 Loop control in a data processor 失效
标题翻译：在einem Datenprozessor的Schleifensteuerung。
公开(公告)号：EP0511484A2
公开(公告)日：1992-11-04
申请号：EP92104507.6
申请日：1992-03-16
申请人： HITACHI, LTD.
发明人： Okado, Kazuo , Sugino, Kimihiro
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/26 , G06F9/325
摘要： Disclosed is a data processor comprising a micro ROM 201, an instruction decoder 1DEC, a repeat controller 207 and a first and a second instruction register IR1, IR2. The instruction decoder 1DEC decodes a repeat instruction read from the micro ROM 201 and thereby furnishes the repeat controller 207 with an internal state requiring specific instructions following the repeat instruction to be executed repeatedly. In turn, the repeat controller 207 reads the instructions to be repeated in series from the micro ROM 201 and places them into the first and second instruction registers IR1, IR2 for execution. Then with access to the micro ROM 201 inhibited, the instructions in the first and second instruction registers IR1, IR2 are supplied repeatedly to the instruction decoder 1DEC for recurrent execution until a repeat counter RC within the repeat controller 207 returns to zero.
摘要翻译：公开了一种数据处理器，其包括微ROM 201，指令解码器1DEC，重复控制器207以及第一和第二指令寄存器IR1，IR2。指令解码器1DEC解码从微ROM 201读取的重复指令，从而向重复控制器207提供需要重复执行的重复指令之后的特定指令的内部状态。反过来，重复控制器207读取从微ROM 201串行重复的指令，并将它们放入第一和第二指令寄存器IR1，IR2中以供执行。然后，对微ROM 201的访问被禁止，第一和第二指令寄存器IR1，IR2中的指令被重复地提供给指令解码器1DEC，用于循环执行，直到重复控制器207内的重复计数器RC返回到零。

2. 发明公开

EP0515057A2 Semiconductor integrated device for echo cancelling 失效
标题翻译： Integrierte Halbleiterschaltung zur Echokompensation。
公开(公告)号：EP0515057A2
公开(公告)日：1992-11-25
申请号：EP92304043.0
申请日：1992-05-05
申请人： HITACHI, LTD.
发明人： Takeuchi, Yusuke , Kokubo, Masaru , Yabuta, Keizo , Kenmoku, Atuko , Okado, Kazuo
IPC分类号： H04B3/23
CPC分类号： H04B3/23
摘要： A sending data buffer for holding sending data temporarily and transmitting the data to an echo canceler section is installed between a sending section and an echo canceler section of an echo canceler integrated circuit included in a subscriber line circuit of the integrated service digital network. The sending data buffer is operated in shift register mode in sending training mode, and operated in FIFO (first in first out) mode in sending/receiving training mode. Also adjustment function of the delay amount corresponding to the use setting is added.
摘要翻译：用于暂时保持发送数据的发送数据缓冲器被安装在综合业务数字网络的用户线电路中的回波消除器集成电路的发送部分和回波消除器部分之间，并将数据发送到回波消除器部分。发送数据缓冲器在发送训练模式下以移位寄存器模式运行，并在发送/接收训练模式下以FIFO（先进先出）模式运行。还增加了与使用设置对应的延迟量的调整功能。

3. 发明公开

EP0515057A3 Semiconductor integrated device for echo cancelling 失效
标题翻译：用于ECHO取消的半导体集成器件
公开(公告)号：EP0515057A3
公开(公告)日：1994-05-18
申请号：EP92304043.0
申请日：1992-05-05
申请人： HITACHI, LTD.
发明人： Takeuchi, Yusuke , Kokubo, Masaru , Yabuta, Keizo , Kenmoku, Atuko , Okado, Kazuo
IPC分类号： H04B3/23
CPC分类号： H04B3/23
摘要： A sending data buffer for holding sending data temporarily and transmitting the data to an echo canceler section is installed between a sending section and an echo canceler section of an echo canceler integrated circuit included in a subscriber line circuit of the integrated service digital network. The sending data buffer is operated in shift register mode in sending training mode, and operated in FIFO (first in first out) mode in sending/receiving training mode. Also adjustment function of the delay amount corresponding to the use setting is added.

4. 发明公开

EP0511484A3 Loop control in a data processor 失效
标题翻译：数据处理器中的环路控制
公开(公告)号：EP0511484A3
公开(公告)日：1994-05-11
申请号：EP92104507.6
申请日：1992-03-16
申请人： HITACHI, LTD.
发明人： Okado, Kazuo , Sugino, Kimihiro
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/26 , G06F9/325
摘要： Disclosed is a data processor comprising a micro ROM 201, an instruction decoder 1DEC, a repeat controller 207 and a first and a second instruction register IR1, IR2. The instruction decoder 1DEC decodes a repeat instruction read from the micro ROM 201 and thereby furnishes the repeat controller 207 with an internal state requiring specific instructions following the repeat instruction to be executed repeatedly. In turn, the repeat controller 207 reads the instructions to be repeated in series from the micro ROM 201 and places them into the first and second instruction registers IR1, IR2 for execution. Then with access to the micro ROM 201 inhibited, the instructions in the first and second instruction registers IR1, IR2 are supplied repeatedly to the instruction decoder 1DEC for recurrent execution until a repeat counter RC within the repeat controller 207 returns to zero.

5. 发明公开

EP0506094A3 A semiconductor integrated circuit and a data processor 失效
标题翻译：半导体集成电路和数据处理器
公开(公告)号：EP0506094A3
公开(公告)日：1994-06-15
申请号：EP92105324.5
申请日：1992-03-27
申请人： HITACHI, LTD.
发明人： Okado, Kazuo , Akojima, Chikara , Kenmoku, Atuko , Sugino, Kimihiro
IPC分类号： G06J1/00 , H04B3/23
CPC分类号： H03M3/376 , G06J1/00 , H03M3/458
摘要： In a digital-analog hybrid LSI including an analog circuit (2) and a digital circuit (3), the analog circuit (2) includes a circuit for sampling, according to the operation timing of a switch (4), information to be processed by the analog circuit (2) in a capacitor (5). A clock signal generating means (6) generates an operation reference clock signal (b) for the digital circuit (3) so that the change of the clock signal (b) is stopped at a timing when the switch (4) is opened, i.e., during a specified period (T) which includes the high-to-low transition timing of the clock signal. This prevents the analog characteristic of the analog circuit (3) from being degraded by digital noise that is transferred through the junction capacitance of the semiconductor chip (1).

6. 发明公开

EP0506094A2 A semiconductor integrated circuit and a data processor 失效
标题翻译： Halbleiterintegrierte Schaltung和Datenprozessor。
公开(公告)号：EP0506094A2
公开(公告)日：1992-09-30
申请号：EP92105324.5
申请日：1992-03-27
申请人： HITACHI, LTD.
发明人： Okado, Kazuo , Akojima, Chikara , Kenmoku, Atuko , Sugino, Kimihiro
IPC分类号： G06J1/00 , H04B3/23
CPC分类号： H03M3/376 , G06J1/00 , H03M3/458
摘要： In a digital-analog hybrid LSI including an analog circuit (2) and a digital circuit (3), the analog circuit (2) includes a circuit for sampling, according to the operation timing of a switch (4), information to be processed by the analog circuit (2) in a capacitor (5). A clock signal generating means (6) generates an operation reference clock signal (b) for the digital circuit (3) so that the change of the clock signal (b) is stopped at a timing when the switch (4) is opened, i.e., during a specified period (T) which includes the high-to-low transition timing of the clock signal. This prevents the analog characteristic of the analog circuit (3) from being degraded by digital noise that is transferred through the junction capacitance of the semiconductor chip (1).
摘要翻译：在包括模拟电路（2）和数字电路（3）的数模混合式LSI中，模拟电路（2）包括根据开关（4）的操作定时对要处理的信息进行采样的电路通过电容器（5）中的模拟电路（2）。时钟信号发生装置（6）产生用于数字电路（3）的操作基准时钟信号（b），使得时钟信号（b）的改变在开关（4）打开的时刻停止，即，在包括时钟信号的从高到低的转换定时的指定周期（T）期间。这防止了通过半导体芯片（1）的结电容传送的数字噪声来降低模拟电路（3）的模拟特性。

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