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1. 发明申请

WO2012030320A1 MULTILAYER MEMORY ARRAY 审中-公开
标题翻译：多层记忆阵列
公开(公告)号：WO2012030320A1
公开(公告)日：2012-03-08
申请号：PCT/US2010/047115
申请日：2010-08-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , NICKEL, Janice, H. , RIBEIRO, Gilberto, Medeiros , YANG, Jianhua
发明人： NICKEL, Janice, H. , RIBEIRO, Gilberto, Medeiros , YANG, Jianhua
IPC分类号： H01L27/10 , H01L27/115 , H01L21/8247
CPC分类号： G11C13/0007 , G11C5/063 , G11C13/0002 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C2013/0073 , G11C2213/71 , G11C2213/77 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A multilayer crossbar memory array includes a number of layers (514). Each layer (514) includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements (200, 216) disposed at intersections between the top set of parallel lines and the bottom set of parallel lines. A top set of parallel lines from one of the layers (514) is a bottom set of parallel lines for an adjacent one of the layers (514).
摘要翻译：多层交叉存储器阵列包括多个层（514）。每个层（514）包括顶层平行线，与顶层平行线相交的底部平行线组，以及设置在顶部平行线之间的交叉点处的存储元件（200,216）平行线。来自层（514）中的一个的顶层平行线是用于相邻层之一（514）的底部平行线组。

2. 发明申请

WO2011112197A1 DEVICE HAVING MEMRISTIVE MEMORY 审中-公开
标题翻译：具有记忆力的装置
公开(公告)号：WO2011112197A1
公开(公告)日：2011-09-15
申请号：PCT/US2010/027129
申请日：2010-03-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PICKETT, Matthew, D. , YANG, Jianhua , RIBEIRO, Gilberto, Medeiros
发明人： PICKETT, Matthew, D. , YANG, Jianhua , RIBEIRO, Gilberto, Medeiros
IPC分类号： H01L27/115 , H01L21/8247 , G11C16/00
CPC分类号： H01L27/0688 , G11C13/0002 , G11C13/0007 , G11C2213/71 , H01L27/101
摘要： A device (10) may include a semiconductor layer section (25) and a memory layer section (45) disposed above the semiconductor layer section (25). The semiconductor layer section (25) may include a processor (12; 412) and input/output block (16; 416), and the memory layer section (45) may include memristive memory (14; 300). A method of forming such device (10), and an apparatus (600) including such device (10) are also disclosed. Other embodiments are described and claimed.
摘要翻译：器件（10）可以包括设置在半导体层部分（25）上方的半导体层部分（25）和存储层部分（45）。半导体层部分（25）可以包括处理器（12; 412）和输入/输出块（16; 416），并且存储器层部分（45）可以包括忆阻存储器（14; 300）。还公开了形成这种装置（10）的方法，以及包括这种装置（10）的装置（600）。描述和要求保护其他实施例。

3. 发明申请

WO2010144097A1 HIERARCHICAL ON-CHIP MEMORY 审中-公开
标题翻译：分层片上记忆
公开(公告)号：WO2010144097A1
公开(公告)日：2010-12-16
申请号：PCT/US2009/047253
申请日：2009-06-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , RIBEIRO, Gilberto, Medeiros , WILLIAMS, R., Stanley , PICKETT, Matthew, D.
发明人： RIBEIRO, Gilberto, Medeiros , WILLIAMS, R., Stanley , PICKETT, Matthew, D.
IPC分类号： H01L23/12 , G11C5/02
CPC分类号： G11C5/02 , G11C5/063 , G11C2213/71
摘要： A hierarchical on-chip memory (400) includes an area distributed CMOS layer (310) comprising input/output functionality and volatile memory and via array (325, 330), the area distributed CMOS layer (310) configured to selectively address the via array (325, 330). A crossbar memory (305) overlies the area distributed CMOS layer (310) and includes programmable crosspoint devices (315) which are uniquely accessed through the via array (325, 330). A method for utilizing hierarchical on-chip memory (400) includes storing frequently rewritten data in a volatile memory and storing data which is not frequently rewritten in a non-volatile memory (305), where the volatile memory is contained within an area distributed CMOS layer (310) and the non-volatile memory (305) is formed over and accessed through the area distributed CMOS layer (310).
摘要翻译：分层片上存储器（400）包括包括输入/输出功能的区域分布式CMOS层（310）和易失性存储器和通孔阵列（325,330），所述区域分布式CMOS层（310）被配置为选择性地寻址通孔阵列（325,330）。交叉开关存储器（305）覆盖区域分布式CMOS层（310），并且包括通过通孔阵列（325,330）唯一访问的可编程交叉点设备（315）。一种用于利用分层片上存储器（400）的方法包括：将经常重写的数据存储在易失性存储器中，并将非频繁重写的数据存储在非易失性存储器（305）中，其中易失性存储器包含在区域分布式CMOS 层（310）和非易失性存储器（305）形成在区域分布式CMOS层（310）上并通过区域分布式CMOS层（310）访问。

4. 发明公开

EP2612357A1 MULTILAYER MEMORY ARRAY 审中-公开
标题翻译：多层存储阵列
公开(公告)号：EP2612357A1
公开(公告)日：2013-07-10
申请号：EP10856793.4
申请日：2010-08-30
申请人： Hewlett-Packard Development Company, L.P.
发明人： NICKEL, Janice, H. , RIBEIRO, Gilberto, Medeiros , YANG, Jianhua
IPC分类号： H01L27/10 , H01L27/115 , H01L21/8247
CPC分类号： G11C13/0007 , G11C5/063 , G11C13/0002 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C2013/0073 , G11C2213/71 , G11C2213/77 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A multilayer crossbar memory array includes a number of layers (514). Each layer (514) includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements (200, 216) disposed at intersections between the top set of parallel lines and the bottom set of parallel lines. A top set of parallel lines from one of the layers (514) is a bottom set of parallel lines for an adjacent one of the layers (514).

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