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1. 发明申请

WO2006083310A2 NANOWIRE DEVICE WITH (111) VERTICAL SIDEWALLS AND METHOD OF FABRICATION 审中-公开
标题翻译：具有（111）垂直侧壁的纳米线装置和制造方法
公开(公告)号：WO2006083310A2
公开(公告)日：2006-08-10
申请号：PCT/US2005/022699
申请日：2005-06-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ISLAM, Saiful, M. , CHEN, Yong , WANG, Shih-Yuan
发明人： ISLAM, Saiful, M. , CHEN, Yong , WANG, Shih-Yuan
IPC分类号： B81B7/00
CPC分类号： H01L27/1203 , B82Y10/00 , G11C2213/81 , H01L29/045 , H01L29/0665 , H01L29/0673 , H01L29/861
摘要： A nano-scale device 10, 20, 30, 60 and method 40, 50, 70 of fabrication provide a nanowire 14, 24, 34, 64 having (111) vertical sidewalls 14a, 22e, 34a, 64a. The nano-scale device includes a semiconductor-on-insulator substrate 12, 22, 32, 62 polished in a [110] direction, the nanowire, and an electrical contact 26, 35 at opposite ends of the nanowire 24, 34. The method 40, 50, 70 includes wet etching 42, 52, 72 a semiconductor layer 12a, 22a, 32a. 62a of the semiconductor-on-insulator substrate to form 44, 54 the nanowire 24, 34 extending between a pair of islands 22f, 32f in the semiconductor layer 22a, 32a. The method 50 further includes depositing 56 an electrically conductive material on the pair of islands to form the electrical contacts 26, 36. A nano-pn diode 60 includes the nanowire 64 as a first nano-electrode, a pn-junction 66 verically stacked on the nanowire 64, and a second nano-electrode 68 on a (110) horizontal planar end of the pn-junction. The nano-pn diode 60 may be fabricated in array of the diodes on the semiconductor-on-insulator substrate 62.
摘要翻译：纳米级器件10,20,30,60和制造方法40,50,70提供纳米线14,24,34,64，其具有（111）垂直侧壁14a，22e，34a ，64a。纳米级器件包括在[110]方向上抛光的绝缘体上半导体衬底12,22,32,62，纳米线以及在纳米线24,34的相对端处的电接触26,35。方法 40,50,70包括湿法刻蚀42,52,72半导体层12a，22a，32a。 62a以形成在半导体层22a，32a中的一对岛22f，32f之间延伸的纳米线24,34。方法50进一步包括在这对岛上沉积56导电材料以形成电接触26,36。纳米pn二极管60包括作为第一纳米电极的纳米线64，静电堆叠在其上的pn结66 纳米线64以及在pn结的（110）水平平面端上的第二纳米电极68。纳米pn二极管60可以在绝缘体上半导体衬底62上的二极管阵列中制造。

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