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1. 发明申请

WO2016018404A1 DETERMINING A RESISTANCE STATE OF A CELL IN A CROSSBAR MEMORY ARRAY 审中-公开
标题翻译：确定一个细胞在电阻记忆阵列中的电阻状态
公开(公告)号：WO2016018404A1
公开(公告)日：2016-02-04
申请号：PCT/US2014/049271
申请日：2014-07-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： MURALIMANOHAR, Naveen , ORDENTLICH, Erik
IPC分类号： G11C7/04 , G11C7/10
CPC分类号： G11C13/004 , G11C13/0002 , G11C13/0007 , G11C27/02 , G11C2013/0042 , G11C2013/0045 , G11C2013/0057
摘要： According to an example, in a method for determining a resistance state of a cell in a crossbar memory array, a first read voltage may be applied across a cell to sense a first cell current. In addition, a second read voltage may be applied across the cell to sense a second cell current. A difference value between the first cell current and the second cell current may be identified and a resistance state of the cell may be determined based on the difference value.
摘要翻译：根据一个示例，在用于确定交叉开关存储器阵列中的单元的电阻状态的方法中，可以跨单元施加第一读取电压以感测第一单元电流。此外，可以跨单元施加第二读取电压以感测第二单元电流。可以识别第一电池电流和第二电池电流之间的差值，并且可以基于差值来确定电池的电阻状态。

2. 发明申请

WO2013015805A1 EFFICIENT DATA-STORAGE DEVICES THAT INCLUDE MEMORY ELEMENTS CHARACTERIZED BY POTENTIALLY LARGE SWITCHING LATENCIES 审中-公开
标题翻译：有效的数据存储设备，其中包含潜在的大开关延迟表示的存储器元件
公开(公告)号：WO2013015805A1
公开(公告)日：2013-01-31
申请号：PCT/US2011/045549
申请日：2011-07-27
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ORDENTLICH, Erik , SEROUSSI, Gadiel
发明人： ORDENTLICH, Erik , SEROUSSI, Gadiel
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G06F11/10 , G06F11/1008 , G11C7/04 , G11C7/1006 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2211/5624
摘要： One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements that each includes a data-storage medium that is switched between two different states by application of a switching-inducing force or gradient to the data-storage medium, a top control element and a bottom control element through which the switching-inducing force or gradient is applied, and a feedback signal. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force to the one or more arrays of memory elements until feedback signals indicate that the WRITE operation has completed or until the switching-inducing force or gradient has been applied for a maximum application time.
摘要翻译：应用中公开的一个示例是电子数据存储设备，其包括一个或多个存储器单元阵列，每个存储器单元阵列包括通过向数据存储器件施加切换诱导力或梯度而在两种不同状态之间切换的数据存储介质，存储介质，通过其施加开关诱导力或梯度的顶部控制元件和底部控制元件以及反馈信号。数据存储装置还包括对接收到的数据进行编码的错误控制编码编码器和通过应用切换诱导力将从错误控制编码编码器接收的编码数据写入多个存储元件的读/写控制器到一个或多个存储器元件阵列，直到反馈信号指示WRITE操作已经完成或者直到在最大应用时间施加了转换诱导力或梯度。

3. 发明申请

WO2015116203A1 ENCODED CROSS-POINT ARRAY 审中-公开
标题翻译：编码交叉点阵列
公开(公告)号：WO2015116203A1
公开(公告)日：2015-08-06
申请号：PCT/US2014/014272
申请日：2014-01-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： LESARTRE, Gregg , GIBSON, Gary , ORDENTLICH, Erik , JEON, Yoocharn
IPC分类号： H04N19/00
CPC分类号： G11C13/003 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/77 , H01L27/2463
摘要： A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.
摘要翻译：一种设备包括交叉点阵列和访问电路，以访问分别对应于编码的数据块的存储器元件的子集。对于存储器元件的每个子集，包括子集中的第一存储器元件和该子集中的第二存储器元件的交叉点阵列的行或列还包括位于第一和第二存储器元件之间的第三存储器元件沿着行或列的存储器元件，并且在对应于另一编码块的子集之一中。

4. 发明申请

WO2012015389A1 METHOD AND SYSTEM FOR COMPRESSING BITPLANES BASED ON BIT POSITION 审中-公开
标题翻译：基于位位置压缩BITPLAN的方法和系统
公开(公告)号：WO2012015389A1
公开(公告)日：2012-02-02
申请号：PCT/US2010/043275
申请日：2010-07-26
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , SEROUSSI, Gadiel , WEINBERGER, Marcelo , ETKIN, Raul Hernan , ORDENTLICH, Erik
发明人： SEROUSSI, Gadiel , WEINBERGER, Marcelo , ETKIN, Raul Hernan , ORDENTLICH, Erik
IPC分类号： H04W52/02 , H04W28/06 , H04L12/28
CPC分类号： H04W52/0209 , H04L67/12 , H04W4/38 , H04W52/0251 , Y02D70/00
摘要： A technology is provided for compressing digital discrete node data to reduce overall power consumption. Node data can be represented by a plurality of data units with a specified data width and can also be viewed as a plurality of bit planes corresponding to data at each bit position for the data units (710). A threshold bit position value may be selected for data units using an achievable compressibility estimate relative to an estimated energy consumption (720). The threshold bit position value can represent a boundary where an estimated energy consumption for compressing and transmitting a bit plane is less than an estimated energy consumption for transmitting the bit plane uncompressed (730). A bit plane is selected in the plurality of bit planes with a bit position value greater than the threshold bit position value (740). The bit plane is compressed using a compressor in the networked node (750).
摘要翻译：提供了一种用于压缩数字离散节点数据以减少总功耗的技术。节点数据可以由具有指定数据宽度的多个数据单元表示，并且还可以被视为与数据单元（710）的每个位位置处的数据相对应的多个位平面。可以使用相对于估计的能量消耗的可实现的可压缩性估计来为数据单元选择阈值位置值（720）。阈值位位置值可以表示用于压缩和发送位平面的估计能量消耗小于用于发送未压缩的位平面的估计能量消耗的边界（730）。在位位置值大于阈值位位置值的多个位平面中选择位平面（740）。使用网络节点（750）中的压缩器对位平面进行压缩。

5. 发明申请

WO2009059067A3 DATA SEQUENCE COMPRESSION 审中-公开
公开(公告)号：WO2009059067A3
公开(公告)日：2009-05-07
申请号：PCT/US2008/081882
申请日：2008-10-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ORDENTLICH, Erik , WEINBERGER, Marcelo
发明人： ORDENTLICH, Erik , WEINBERGER, Marcelo
IPC分类号： H04N7/50
摘要： In a method of compressing a data sequence, the data sequence is parsed (302) into data segments, where at least one of the data segments includes a match. In addition, the match is compressed (304) using at least one context model that depends upon one or more coded data symbols that are available to a decoder (250). An encoder (200) includes a coding unit (222, 224, 226) configured to code at least one of a match offset and a match length of a data segment using one or more context models that depend on previously decodeable data symbols. A computer readable storage medium having a computer program for implementing the method (300, 320) of compressing the data sequence.

6. 发明申请

WO2006012349A1 DISCRETE UNIVERSAL DENOISING WITH RELIABILITY INFORMATION 审中-公开
标题翻译：具有可靠性信息的通用型通信
公开(公告)号：WO2006012349A1
公开(公告)日：2006-02-02
申请号：PCT/US2005/022599
申请日：2005-06-24
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , WEISSMAN, Itschak , ORDENTLICH, Erik , SEROUSSI, Gadiel , VERDU, Sergio , WEINBERGER, Marcelo , VISWANATHAN, Krishnamurthy
发明人： WEISSMAN, Itschak , ORDENTLICH, Erik , SEROUSSI, Gadiel , VERDU, Sergio , WEINBERGER, Marcelo , VISWANATHAN, Krishnamurthy
IPC分类号： H04L25/06
CPC分类号： H04L1/0045 , H04L25/067
摘要： A method of and system for generating reliability information (1616) for a noisy signal (1612) received through a noise-introducing channel (1606). In one embodiment, symbol-transition probabilities are determined for the noise-introducing channel (1606). Occurrences of metasymbols in the noisy signal (1612) are counted, each metasymbol providing a context for a symbol of the metasymbol. For each metasymbol occuring in the noisy signal, reliability information (1616) for each possible value of the symbol of the metasymbol is determined, the reliability information (1616) representing a proability that the value in the original signal corresponding to the symbol of the metasymbol assumed each of the possible values. In another embodiment, error correction coding may be performed by adding redundant data to an original signal prior (1600) to transmission by the noise-introducing channel (1606) and performing error correction decoding after transmission.
摘要翻译：一种用于产生通过噪声引入通道（1606）接收的噪声信号（1612）的可靠性信息（1616）的方法和系统。在一个实施例中，为噪声引入信道（1606）确定符号转换概率。在嘈杂信号（1612）中发生met符号的发生，每个符号都提供符号的符号的上下文。对于在噪声信号中发生的每个元符号，确定对于符号的符号的每个可能值的可靠性信息（1616），表示对应于符号的符号的原始信号中的值的可靠性信息（1616）假设每个可能的值。在另一个实施例中，纠错编码可以通过在（1600）之前将原始信号添加到由噪声引入信道（1606）进行传输并在传输之后执行纠错解码来执行。

7. 发明申请

WO2016018386A1 ENCODING DATA WITHIN A CROSSBAR MEMORY ARRAY 审中-公开
标题翻译：在十字架内存区域中编码数据
公开(公告)号：WO2016018386A1
公开(公告)日：2016-02-04
申请号：PCT/US2014/049205
申请日：2014-07-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： MURALIMANOHAR, Naveen , ORDENTLICH, Erik , XU, Cong
IPC分类号： G06F12/00
CPC分类号： G06F3/0638 , G06F3/0604 , G06F3/0679 , G11C7/1012 , G11C13/0069 , G11C2213/77
摘要： In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.
摘要翻译：在一个示例中，在用于对包含单元的交叉开关存储器阵列内的数据进行编码的方法中，可以接收输入数据的位。所接收的数据位可以被映射到存储器阵列的行中的单元，其中单元将被分配到低电阻状态和高电阻状态之一。行中的映射比特的一个子集可以被分组成一个单词模式。字图案可以被布置为使得更低的电阻状态被映射到位于更靠近存储器阵列的电压源的单元，而不是位于远离电压源的单元。

8. 发明申请

WO2015116084A1 DATA STORING IN MEMORY ARRAYS 审中-公开
标题翻译：数据存储在存储器阵列中
公开(公告)号：WO2015116084A1
公开(公告)日：2015-08-06
申请号：PCT/US2014/013764
申请日：2014-01-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： ORDENTLICH, Erik , ROTH, Ron M
IPC分类号： G11C13/00
CPC分类号： G06F17/30 , G06F3/0604 , G06F3/0638 , G06F3/0679 , G11C13/0007 , G11C13/004 , G11C13/0069
摘要： Methods and systems for storing data in memory arrays are described. In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes the input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.
摘要翻译：描述了将数据存储在存储器阵列中的方法和系统。在一个实现中，数据存储系统包括具有交叉开关配置的存储器件的存储器阵列和用于控制存储器阵列中的数据存储的存储器控制器。存储器控制器包括编码器，用于产生对输入数据进行编码的2维编码位模式。编码比特模式的每行或每列的每个游程长度为0，每个游程长度为1，至少为预定义的下限。预定义的下限至少为2。存储器控制器包括写控制器，用于将编码位模式写入存储器阵列的存储器件，使得存储器阵列的每行或每列中具有相同状态的多个连续存储器件基于编码位模式。

9. 发明申请

WO2013015803A1 METHOD AND SYSTEM FOR REDUCING WRITE-BUFFER CAPACITIES WITHIN MEMRISTOR-BASED DATA-STORAGE DEVICES 审中-公开
标题翻译：用于减少基于机器人的数据存储设备中的写缓冲器容量的方法和系统
公开(公告)号：WO2013015803A1
公开(公告)日：2013-01-31
申请号：PCT/US2011/045529
申请日：2011-07-27
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ORDENTLICH, Erik , SEROUSSI, Gadiel
发明人： ORDENTLICH, Erik , SEROUSSI, Gadiel
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G06F11/10 , G06F11/1048 , G11C7/1006 , G11C7/1078 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2211/5624
摘要： One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, until feedback signals indicate that the WRITE operation has completed, or until the switching-inducing force or gradient has been applied for a maximum application time.
摘要翻译：应用中公开的一个示例是包括一个或多个存储器元件阵列的电子数据存储设备。数据存储装置还包括对接收到的数据进行编码的错误控制编码编码器和读/写控制器，该读/写控制器通过应用切换诱导力将从误差控制编码编码器接收的编码数据写入多个存储元件或梯度到存储器元件的一个或多个阵列，直到写入请求缓冲器已被排队等于多于一个最大允许数量的WRITE请求缓冲器，直到反馈信号指示写入操作已经完成，或者直到开关诱导力或梯度已应用于最大应用时间。

10. 发明申请

WO2011112201A1 CODING FOR CROSSBAR ARCHITECTURE 审中-公开
标题翻译：交叉建筑编码
公开(公告)号：WO2011112201A1
公开(公告)日：2011-09-15
申请号：PCT/US2010/027227
申请日：2010-03-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , ORDENTLICH, Erik , ROTH, Ron M.
发明人： ORDENTLICH, Erik , ROTH, Ron M.
IPC分类号： G06F5/00 , G06F7/00 , G06F9/00
CPC分类号： G11C13/0002 , G11C2213/77
摘要： A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system (100), a subset of crosspoints (306) within a crossbar matrix (300), the crossbar matrix (300) comprising a number of disjointed intersecting wire segments (302, 304), the subset corresponding to a predetermined path (408) through the crossbar matrix (300); and encoding, with the physical computing system (100), a number of data bits (502) to be placed along the predetermined path (408); in which the encoding causes bits pertaining to at least one of the wire segments (302, 304) to be subject to a constraint when the data bits (502) are placed along the predetermined path (408).
摘要翻译：用于编码要存储在由物理计算系统执行的交叉开关存储器架构中的位的位的方法包括：使用所述物理计算系统（100）指定交叉矩阵（300）内的交叉点（306）的子集，所述交叉矩阵（ 300）包括多个不相交的相交线段（302,304），所述子集对应于通过所述交叉矩阵（300）的预定路径（408）; 以及用所述物理计算系统（100）编码要沿着所述预定路径（408）放置的多个数据比特（502）; 其中当沿着预定路径（408）放置数据位（502）时，编码导致与至少一个有线段（302,304）有关的位受到约束。

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