专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011094437A2 MEMORY ACCESS METHODS AND APPARATUS 审中-公开
标题翻译：存储器访问方法和设备
公开(公告)号：WO2011094437A2
公开(公告)日：2011-08-04
申请号：PCT/US2011022763
申请日：2011-01-27
申请人： HEWLETT PACKARD DEVELOPMENT CO , UNIV UTAH RES FOUND , MURALIMANOHAR NAVEEN , UDIPI ANIRUDDHA , CHATTERJEE NILADRISH , BALASUBRAMONIAN RAJEEV , DAVIS ALAN LYNN , JOUPPI NORMAN PAUL
发明人： MURALIMANOHAR NAVEEN , UDIPI ANIRUDDHA , CHATTERJEE NILADRISH , BALASUBRAMONIAN RAJEEV , DAVIS ALAN LYNN , JOUPPI NORMAN PAUL
IPC分类号： G11C11/4063 , G06F12/00 , G11C7/10
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02B60/1225 , Y02D10/13
摘要： A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
摘要翻译：所公开的示例性装置包括用于将对应于行（608）的行地址存储在存储器阵列（602）中的行地址寄存器（412）。示例性装置还包括耦合到行地址寄存器的行解码器（604），用于在存储器接收列地址之后，在行的字线（704）上断言信号。另外，示例性装置包括列解码器（606），用于基于列地址和在字线上断言的信号选择性地激活该行的一部分。

2. 发明申请

WO2011094436A3 INTERFACE METHODS AND APPARATUS FOR MEMORY DEVICES 审中-公开
标题翻译：用于存储器件的接口方法和装置
公开(公告)号：WO2011094436A3
公开(公告)日：2011-11-24
申请号：PCT/US2011022762
申请日：2011-01-27
申请人： HEWLETT PACKARD DEVELOPMENT CO , MURALIMANOHAR NAVEEN , JOUPPI NORMAN PAUL
发明人： MURALIMANOHAR NAVEEN , JOUPPI NORMAN PAUL
IPC分类号： G06F13/16 , G06F12/00 , G06F13/38
CPC分类号： G06F13/161 , G06F12/0804 , G06F13/1642
摘要： A disclosed example apparatus includes an interface (702, 726) to receive a request to access a memory (602a) of a memory module (600) and a data store status monitor (730) to determine a status of the memory. The example apparatus also includes a message output subsystem (732) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.
摘要翻译：所公开的示例性设备包括接收访问存储器模块（600）的存储器（602a）的请求的接口（702,726）和用于确定存储器的状态的数据存储状态监视器（730）。示例性装置还包括消息输出子系统（732），当存储器正忙时，以指示存取存取器的请求不可授予的否定确认来响应该请求。

3. 发明公开

EP2529374A4 MEMORY ACCESS METHODS AND APPARATUS 审中-公开
标题翻译：存储器访问方法和装置
公开(公告)号：EP2529374A4
公开(公告)日：2014-04-02
申请号：EP11737663
申请日：2011-01-27
申请人： HEWLETT PACKARD DEVELOPMENT CO , UNIV UTAH RES FOUND
发明人： MURALIMANOHAR NAVEEN , UDIPI ANIRUDDHA NAGENDRAN , CHATTERJEE NILADRISH , BALASUBRAMONIAN RAJEEV , DAVIS ALAN LYNN , JOUPPI NORMAN PAUL
IPC分类号： G11C11/4063 , G06F12/00 , G11C7/10
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02B60/1225 , Y02D10/13
摘要： An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

4. 发明专利

DE112011105706T5 Zeilenverschiebender verschiebbarer Speicher 未知
公开(公告)号：DE112011105706T5
公开(公告)日：2014-07-10
申请号：DE112011105706
申请日：2011-10-28
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： BOEHM HANS , MURALIMANOHAR NAVEEN
IPC分类号： G11C19/00 , G11C7/10
摘要： Ein verschiebbarer Speicher setzt Zeilenverschiebung ein, um Daten entlang einer Zeile zu verschieben. Der verschiebbare Speicher umfasst Speicherzellen, die als eine Vielzahl von Zeilen und eine Vielzahl von Spalten angeordnet sind. Der verschiebbare Speicher umfasst weiter Verschiebelogik, um Daten von einem Ausgang einer ersten Spalte zu einem Eingang einer zweiten Spalte zu verschieben. Die verschobenen Daten werden von einer Speicherzelle der ersten Spalte in einer ausgewählten Zeile bereitgestellt. Die verschobenen Daten werden von einer Speicherzelle in der ausgewählten Zeile der zweiten Spalte empfangen und gespeichert. Die Verschiebelogik vereinfacht das Verschieben von Daten entlang der ausgewählten Zelle.

5. 发明专利

GB2510286A Row shifting shiftable memory 未知
公开(公告)号：GB2510286A
公开(公告)日：2014-07-30
申请号：GB201407330
申请日：2011-10-28
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： MURALIMANOHAR NAVEEN , BOEHM HANS
IPC分类号： G11C19/18 , G11C7/10 , G11C11/408 , G11C11/418 , G11C19/00 , G11C19/28
摘要： A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.

6. 发明专利

GB2510286B Row shifting shiftable memory 未知
公开(公告)号：GB2510286B
公开(公告)日：2015-08-19
申请号：GB201407330
申请日：2011-10-28
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： MURALIMANOHAR NAVEEN , BOEHM HANS
IPC分类号： G11C19/18 , G11C7/10 , G11C11/408 , G11C11/418 , G11C19/00 , G11C19/28
摘要： A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.

7. 发明申请

WO2015116158A3 ENCODING DATA IN A MEMORY ARRAY 审中-公开
标题翻译：在存储阵列中编码数据
公开(公告)号：WO2015116158A3
公开(公告)日：2015-11-26
申请号：PCT/US2014014124
申请日：2014-01-31
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： LESARTRE GREGG B , MURALIMANOHAR NAVEEN , JEON YOOCHARN
IPC分类号： G11C16/08 , G11C7/10 , G11C16/34
CPC分类号： G06F3/0619 , G06F3/0625 , G06F3/065 , G06F3/0689 , G06F12/023 , G06F2212/1028 , G06F2212/1036 , G06F2212/401 , G11C7/1006 , Y02D10/13
摘要： A method for encoding data in a memory array is described. The method includes receiving data to be stored in the memory array. The method also includes encoding the data, to generate a number of encoded data versions. The method also includes selecting, based on a number of optimization heuristics, which of a number of data versions to store in the memory array. The number of data versions include the number of encoded data versions and the data. The method also includes indicating, in metadata associated with the data, the selected data version. The method also includes writing the selected data version, the metadata, or combination thereof, to the memory array.
摘要翻译：描述了用于在存储器阵列中编码数据的方法。该方法包括接收要存储在存储器阵列中的数据。该方法还包括编码数据，以生成多个编码的数据版本。该方法还包括基于多个优化启发式来选择要存储在存储器阵列中的多个数据版本中的哪一个。数据版本的数量包括编码数据版本的数量和数据。该方法还包括在与数据相关联的元数据中指示所选数据版本。该方法还包括将选择的数据版本，元数据或其组合写入存储器阵列。

8. 发明申请

WO2015116133A3 REMAPPING MEMORY LOCATIONS IN A MEMORY ARRAY 审中-公开
标题翻译：存储器阵列中的重复存储器位置
公开(公告)号：WO2015116133A3
公开(公告)日：2015-11-19
申请号：PCT/US2014014018
申请日：2014-01-31
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： LESARTRE GREGG B , MURALIMANOHAR NAVEEN
IPC分类号： G11C29/44 , G06F11/07
CPC分类号： G11C29/76 , G06F11/1004 , G06F12/0223 , G06F2212/1032 , G11C29/12 , G11C29/82 , G11C2029/4402
摘要： A method for remapping a memory location in a memory array is described. The method includes receiving, by a memory manager, an identification of a first memory location in a memory array that is to be remapped using a remapping procedure performed by a memory manager. The remapping procedure includes selecting a second memory location to store data intended for the first memory location. The procedure also includes writing, in the first memory location, a pointer to the second memory location.
摘要翻译：描述了用于重新映射存储器阵列中的存储器位置的方法。该方法包括由存储器管理器接收存储器阵列中的第一存储器位置的标识，该第一存储器位置将使用由存储器管理器执行的重新映射过程来重映射。重新映射过程包括选择第二存储位置以存储预期用于第一存储位置的数据。该过程还包括在第一存储位置写入指向第二存储位置的指针。

9. 发明公开

EP2901457A4 DYNAMICALLY SELECTING BETWEEN MEMORY ERROR DETECTION AND MEMORY ERROR CORRECTION 审中-公开
标题翻译：之间的内存错误检测和内存错误纠正动态选择问题
公开(公告)号：EP2901457A4
公开(公告)日：2016-04-13
申请号：EP12885229
申请日：2012-09-28
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： MOGUL JEFFREY CLIFFORD , MURALIMANOHAR NAVEEN , SHAH MEHUL A , ANDERSON ERIC A
IPC分类号： G11C29/42 , G06F11/10
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/0793 , G06F11/1048 , G11C2029/0411

10. 发明公开

EP2859457A4 ACCESSING MEMORY 审中-公开
标题翻译： MEMORY
公开(公告)号：EP2859457A4
公开(公告)日：2016-05-11
申请号：EP12878588
申请日：2012-06-08
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： YOON DOE HYUN , MURALIMANOHAR NAVEEN , CHANG JICHUAN , RANGANTHAN PARTHASARATHY
IPC分类号： G11C5/04 , G06F13/14 , G06F13/16 , G06F13/38 , G11C7/10
CPC分类号： G11C7/1072 , G06F13/1663 , G11C5/04 , G11C2207/108 , G11C2207/2209 , G11C2207/2281 , Y02B60/1228 , Y02D10/14
摘要： A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.
摘要翻译：所公开的示例性方法包括在至少第一和第二独立可选逻辑子列上执行同时数据访问，以通过存储器设备中的宽内部数据总线访问第一数据。存储器件包括转换缓冲器芯片，可独立选择的逻辑子级别的存储器芯片，用于将转换缓冲器芯片连接到存储器控制器的窄外部数据总线，以及翻译缓冲器芯片和存储器芯片之间的宽内部数据总线。仅通过第一可独立选择的逻辑子级执行数据访问，以经由宽内部数据总线访问第二数据。示例性方法还包括在单独的数据传输期间将第一数据的第一部分，第一数据的第二部分和窄的外部数据总线上的第二数据定位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式