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1. 发明公开

EP0712155A3 Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications 失效
标题翻译：一种用于生产掩埋硅化物层和轻掺杂岛和使用之间的欧姆接触过程
公开(公告)号：EP0712155A3
公开(公告)日：1998-01-14
申请号：EP95308026.4
申请日：1995-11-09
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L21/74 , H01L21/20 , H01L21/76 , H01L21/82 , H01L29/08 , H01L29/06
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012 , Y10S148/135
摘要： A buried silicide layer 111 in a bonded wafer 105 makes ohmic contact to a heavily doped buried layer 125. A dopant rapidly diffuses through the silicide layer and into the adjacent semiconductor to form the buried layer.

2. 发明公开

EP0732746A2 Process for doping two levels of a double poly bipolar transistor after formation of second poly layer 失效
标题翻译：过程用于双聚双极型晶体管的两个平面的掺杂
公开(公告)号：EP0732746A2
公开(公告)日：1996-09-18
申请号：EP96301722.3
申请日：1996-03-13
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L27/082 , H01L21/8228
CPC分类号： H01L27/0826 , H01L21/8228 , H01L27/082
摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device and subsequentally doped.
摘要翻译：减小的掩模组，一种用于制造（高频应用）互补双极晶体管结构使用的材料的一个层的几乎横向扩散特性注入复杂的过程，的确是至少一个比在单晶半导体材料的大小为发射极的掺杂剂更高的顺序，单独的基极和发射极多晶硅层未掺杂形成。然后，一个设备的发射极多晶硅和其他装置的基聚边缘通过掺杂剂掩模进行曝光，并同时掺杂。发射掺杂剂直接进入发射极多晶硅的表面，其中它位于其上方并与底座接触。基极接触掺杂物进入基聚的边缘上，包括具有高扩散系数的材料的层，快速扩散尾盘反弹整个做层，然后扩散向下进入收集器的材料（例如冰岛）表面，以形成所述非本征基极，第二掩模被图案化，以暴露所述第二装置的所述发射极和所述第一设备和subsequentally掺杂的基聚的边缘。

3. 发明公开

EP0872884A1 Method and semiconductor device having maximum terminal voltage 失效
标题翻译： Verfahren und Halbleitereinrichtung mit maximaler Terminalspannung
公开(公告)号：EP0872884A1
公开(公告)日：1998-10-21
申请号：EP97302531.5
申请日：1997-04-14
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L21/762 , H01L21/20
CPC分类号： H01L21/763 , H01L21/76264 , H01L21/76286
摘要： A semiconductor island structure with passive side isolation, for reducing corner breakdown where a device conductor crosses the edge of the island. The decrease in the field strength at the island edge between the conductor and the djacent conducting region is by increasing the depth of the insulator beneath the conductor where it crosses the island edge without the necessity tbr increasing the thickness of the layer of insulation applied directly to the surface of the island by the use of a second or higher level interconnect. The decrease in the field strength at the island edge alternatively or in addition be achieved by increasing the thiclmess of the insulator providing lateral isolation without increasing the thickness of the substrate isolation by the use of lateral trench isolation formed independently of the substrate isolation.
摘要翻译：具有被动侧隔离的半导体岛结构，用于减少器件导体跨越岛边缘的拐角击穿。导体与导电区之间的岛边缘处的场强的减小是通过增加导体下方的绝缘子的深度，其中它穿过岛边缘，而不需要增加绝缘层的厚度直接施加到通过使用第二级或更高级互连的岛的表面。岛边缘处的场强的减小可以通过增加提供侧向隔离的绝缘体的开口来实现，而不会通过使用独立于衬底隔离形成的横向沟槽隔离来增加衬底隔离的厚度。

4. 发明公开

EP0732746A3 Process for doping two levels of a double poly bipolar transistor after formation of second poly layer 失效
标题翻译：用于双聚双极型晶体管的两个平面的掺杂工艺，以产生第二级聚
公开(公告)号：EP0732746A3
公开(公告)日：1997-08-20
申请号：EP96301722.3
申请日：1996-03-13
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L27/082 , H01L21/8228
CPC分类号： H01L27/0826 , H01L21/8228 , H01L27/082
摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device and subsequentally doped.
摘要翻译：减小的掩模组，一种用于制造（高频应用）互补双极晶体管结构使用的材料的一个层的几乎横向扩散特性注入复杂的过程，的确是至少一个比在单晶半导体材料的大小为发射极的掺杂剂更高的顺序，单独的基极和发射极多晶硅层未掺杂形成。然后，一个设备的发射极多晶硅和其他装置的基聚边缘通过掺杂剂掩模进行曝光，并同时掺杂。发射掺杂剂直接进入发射极多晶硅的表面，其中它位于其上方并与底座接触。基极接触掺杂物进入基聚的边缘上，包括具有高扩散系数的材料的层，快速扩散尾盘反弹整个做层，然后扩散向下进入收集器的材料（例如冰岛）表面，以形成所述非本征基极，第二掩模被图案化，以暴露所述第二装置的所述发射极和所述第一设备和subsequentally掺杂的基聚的边缘。

5. 发明公开

EP0801426A2 Improved trench MOS gate device and method of producing the same 失效
标题翻译： Verfahren zur Herstellung einer Anordnung mit Graben-MOS-Gate
公开(公告)号：EP0801426A2
公开(公告)日：1997-10-15
申请号：EP97400624.9
申请日：1997-03-20
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L29/78 , H01L29/423 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, having a controlled thickness dimension. These thickness dimensions are related by a controlled floor:sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is at least 1 to 1, and preferably at least 1.2 to 1. A process for forming a trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension, related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1. When silicon dioxide is employed as the dielectric material, the layers preferably comprise a composite of thermally grown and deposited silicon dioxide.
摘要翻译：一种沟槽MOS栅极器件，其包括沟槽，其底层和侧壁包括具有受控厚度尺寸的电介质材料层。这些厚度尺寸通过控制的底板相关：侧壁层厚度比，其通过单独地控制每个地板和侧壁电介质层的厚度来建立。该层至侧壁层的厚度比至少为1比1，优选为至少1.2:1。一种用于形成沟槽MOS栅极器件的工艺包括蚀刻硅器件晶片中的沟槽并在沟槽层上形成电介质材料层并且在侧壁上，每个层具有受控的厚度尺寸，其受控地板至侧壁层厚度比优选为至少1:1。当使用二氧化硅作为电介质材料时，这些层优选包括热生长并沉积二氧化硅。

6. 发明公开

EP0817257A1 Integrated circuit containing devices dielectrically isolated and junction isloated from a substrate 失效
标题翻译：具有介电隔离的装置的集成电路，以及从底物化合物中分离
公开(公告)号：EP0817257A1
公开(公告)日：1998-01-07
申请号：EP97401272.6
申请日：1997-06-06
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L21/76 , H01L27/02
CPC分类号： H01L21/761 , H01L21/76297 , H01L27/0248
摘要： An integrated circuit (200) comprises a plurality of interconnected semiconductor devices, at least one of the interconnected devices (220) being dielectrically isolated from the substrate (201), and at least one other of the interconnected devices (210) being junction isolated from the substrate (201). In an embodiment, at least one of the junction isolated devices comprises an ESD protection circuit (100). The ESD protection circuit (100), includes a zener diode (109) and further includes a bipolar transistor (103), a diode (101), and a resistor (102), is formed in a trench-isolated island (220) comprising a semiconductor layer of a conductivity type opposite to that of the substrate. A heavily doped buried semiconductor region of the same conductivity type as the substrate is formed in the island semiconductor layer adjacent to the substrate.
摘要翻译：集成电路（200）的底物包括互连的半导体器件的复数，所述互连器件中的至少一个（220）被介电离（201）中分离和至少一个其它的互连设备（210），被结分离自基板（201）。中，结隔离装置中的至少一个实施方式中，以在ESD保护电路（100）包括。 ESD保护电路（100）包括一个齐纳二极管（109），并且还包括一个双极型晶体管（103），二极管（101）和电阻（102）在沟槽隔离冰岛（220），其包括形成相反的导电类型的半导体层到基板做的。相同的导电类型作为底物的重掺杂埋半导体区被形成在冰岛半导体层毗邻的基材中形成。

7. 发明公开

EP0712155A2 Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications 失效
标题翻译：一种用于生产掩埋硅化物层和轻掺杂岛和使用之间的欧姆接触过程
公开(公告)号：EP0712155A2
公开(公告)日：1996-05-15
申请号：EP95308026.4
申请日：1995-11-09
申请人： HARRIS CORPORATION
发明人： Beasom, James D.
IPC分类号： H01L21/74 , H01L21/20 , H01L21/76 , H01L21/82 , H01L29/08 , H01L29/06
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012 , Y10S148/135
摘要： A buried silicide layer 111 in a bonded wafer 105 makes ohmic contact to a heavily doped buried layer 125. A dopant rapidly diffuses through the silicide layer and into the adjacent semiconductor to form the buried layer.
摘要翻译：在一键合晶片105的掩埋硅化物层111使欧姆接触的重掺杂掩埋层125掺杂剂迅速通过硅化物层并进入半导体毗邻，以形成掩埋层扩散。

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