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1. 发明授权

US08048812B2 Pitch reduced patterns relative to photolithography features 有权
标题翻译：相对于光刻特征的间距减小
公开(公告)号：US08048812B2
公开(公告)日：2011-11-01
申请号：US12769071
申请日：2010-04-28
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一模式的较小特征。通过图案化无定形碳层来实现间距倍增。然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。将组合图案转移到下面的非晶硅层。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。然后将组合的掩模图案蚀刻到下面的基底中。

2. 发明授权

US07927948B2 Devices with nanocrystals and methods of formation 有权
标题翻译：具有纳米晶体和形成方法的器件
公开(公告)号：US07927948B2
公开(公告)日：2011-04-19
申请号：US11185113
申请日：2005-07-20
申请人： Gurtej S. Sandhu , D. Mark Durcan
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , B82Y10/00 , H01L21/28273 , H01L29/42332 , Y10S438/962
摘要： An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures are grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures include at least one of nanocrystals, nanowires and nanotubes. According to various nanocrystal embodiments, the nanocrystals are positioned within a gate stack and function as a floating gate for a nonvolatile device. Other aspects and embodiments are provided herein.
摘要翻译：一个方面涉及在半导体衬底上生长纳米尺度结构的方法。根据各种实施方案，在基材的表面上形成成核位点。成核位点的产生包括用选择的能量和剂量植入离子，以提供成核位点跨衬底表面的可控分布。使用成核位点的可控分布来生长纳米结构以使纳米尺度结构的生长进行种子生长。根据各种实施方案，纳米尺度结构包括纳米晶体，纳米线和纳米管中的至少一种。根据各种纳米晶体实施例，纳米晶体位于栅极堆叠内并用作非易失性器件的浮动栅极。本文提供了其它方面和实施例。

3. 发明授权

US07557015B2 Methods of forming pluralities of capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US07557015B2
公开(公告)日：2009-07-07
申请号：US11083489
申请日：2005-03-18
申请人： Gurtej S. Sandhu , D. Mark Durcan
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/0805 , Y10T29/43
摘要： The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at least in part with a retaining structure which engages the outer lateral sidewalls. The retaining structure is formed at least in part by etching a layer of material which is not masked anywhere within the capacitor array area to form said retaining structure. The plurality of capacitor electrodes is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成多个电容器的方法。在一个实施方式中，形成多个电容器的方法包括在衬底上的电容器阵列区域内设置多个电容器电极。电容器电极包括外侧壁。多个电容器电极至少部分地具有与外侧向侧壁接合的保持结构。保持结构至少部分地通过蚀刻在电容器阵列区域内的任何地方未被掩蔽的材料层以形成所述保持结构而形成。多个电容器电极被并入多个电容器中。考虑了其他方面和实现。

4. 发明申请

US20070018215A1 Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions 审中-公开
公开(公告)号：US20070018215A1
公开(公告)日：2007-01-25
申请号：US11185186
申请日：2005-12-19
申请人： Gurtej S. Sandhu , D. Mark Durcan
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L27/108 , H01L21/762
CPC分类号： H01L29/0649 , G11C14/0018 , H01L21/76232 , H01L27/10805 , H01L27/11521 , H01L29/0653
摘要： The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

5. 发明申请

US20100210111A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 有权
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：US20100210111A1
公开(公告)日：2010-08-19
申请号：US12769071
申请日：2010-04-28
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/308
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一模式的相对较小的特征。通过图案化无定形碳层来实现间距倍增。然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。将组合图案转移到下面的非晶硅层。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。然后将组合的掩模图案蚀刻到下面的基底中。

6. 发明申请

US20100092891A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 有权
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：US20100092891A1
公开(公告)日：2010-04-15
申请号：US12636581
申请日：2009-12-11
申请人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： G03F7/20
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

7. 发明申请

US20090209080A1 Methods of Forming Pluralities of Capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US20090209080A1
公开(公告)日：2009-08-20
申请号：US12430621
申请日：2009-04-27
申请人： Gurtej S. Sandhu , D. Mark Durcan
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L27/10 , H01G4/30
CPC分类号： H01L28/90 , H01L27/0805 , Y10T29/43
摘要： The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at least in part with a retaining structure which engages the outer lateral sidewalls. The retaining structure is formed at least in part by etching a layer of material which is not masked anywhere within the capacitor array area to form said retaining structure. The plurality of capacitor electrodes is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成多个电容器的方法。在一个实施方式中，形成多个电容器的方法包括在衬底上的电容器阵列区域内设置多个电容器电极。电容器电极包括外侧壁。多个电容器电极至少部分地具有与外侧向侧壁接合的保持结构。保持结构至少部分地通过蚀刻在电容器阵列区域内的任何地方未被掩蔽的材料层以形成所述保持结构而形成。多个电容器电极被并入多个电容器中。考虑了其他方面和实现。

8. 发明申请

US20070235783A9 Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions 审中-公开
标题翻译：半导体结构，存储阵列，电子系统和形成半导体结构的方法
公开(公告)号：US20070235783A9
公开(公告)日：2007-10-11
申请号：US11185186
申请日：2005-07-19
申请人： Gurtej S. Sandhu , D. Mark Durcan
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L27/108 , H01L21/762
CPC分类号： H01L29/0649 , G11C14/0018 , H01L21/76232 , H01L27/10805 , H01L27/11521 , H01L29/0653
摘要： The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
摘要翻译：本发明包括具有沟槽隔离区域的半导体结构。沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。底部可以具有基本上垂直的侧壁，并且可以从侧壁大致垂直延伸的台阶连接到上部。沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。本发明还包括形成半导体结构的方法。

9. 发明授权

US07253118B2 Pitch reduced patterns relative to photolithography features 有权
标题翻译：相对于光刻特征的间距减小
公开(公告)号：US07253118B2
公开(公告)日：2007-08-07
申请号：US11214544
申请日：2005-08-29
申请人： Luan Tran , William T. Rericha , John Lee , Raman Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
发明人： Luan Tran , William T. Rericha , John Lee , Raman Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi (Jenny) Bai , Zhiping Yin , Paul Morgan , Mirzafer K. Abatchev , Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

10. 发明授权

US08501563B2 Devices with nanocrystals and methods of formation 有权
标题翻译：具有纳米晶体和形成方法的器件
公开(公告)号：US08501563B2
公开(公告)日：2013-08-06
申请号：US13614794
申请日：2012-09-13
申请人： Gurtej S. Sandhu , D. Mark Durcan
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , B82Y10/00 , H01L21/28273 , H01L29/42332 , Y10S438/962
摘要： Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.
摘要翻译：可以使用在半导体衬底上生长纳米尺度结构的方法来制造器件。根据各种实施方案，可以在基材的表面上形成成核位点。成核位点的产生可以包括用选择的能量和剂量植入离子，以提供成核位点跨越衬底的表面的可控分布。可以使用成核位点的可控分布来生长纳米尺度结构以使纳米尺度结构的生长生长。根据各种实施方案，纳米级结构可以包括纳米晶体，纳米线或纳米管中的至少一种。根据各种纳米晶体实施例，纳米晶体可以位于栅极堆叠内，并且用作非易失性器件的浮动栅极。本文提供了其他实施例。

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