专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09083441B2 Impedance balancing for transmitter to receiver rejection 有权
标题翻译：用于发射机到接收机拒绝的阻抗平衡
公开(公告)号：US09083441B2
公开(公告)日：2015-07-14
申请号：US13282354
申请日：2011-10-26
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
IPC分类号： H03C1/52 , H04B1/525 , H04B1/58
CPC分类号： H04B1/525 , H04B1/581
摘要： Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.
摘要翻译：示例性实施例涉及收发器内的阻抗平衡。设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。

2. 发明申请

US20130109330A1 IMPEDANCE BALANCING FOR TRANSMITTER TO RECEIVER REJECTION 有权
标题翻译：发射机接收拒绝的阻抗平衡
公开(公告)号：US20130109330A1
公开(公告)日：2013-05-02
申请号：US13282354
申请日：2011-10-26
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
IPC分类号： H04B1/40
CPC分类号： H04B1/525 , H04B1/581
摘要： Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.
摘要翻译：示例性实施例涉及收发器内的阻抗平衡。设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。

3. 发明授权

US08019310B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08019310B2
公开(公告)日：2011-09-13
申请号：US11955201
申请日：2007-12-12
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26 , H04B7/00 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/165 , H03D7/166 , H03D2200/0084 , H03D2200/009
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

4. 发明申请

US20090075620A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：US20090075620A1
公开(公告)日：2009-03-19
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

5. 发明授权

US09362958B2 Single chip signal splitting carrier aggregation receiver architecture 有权
标题翻译：单芯片信号分离载波聚合接收机架构
公开(公告)号：US09362958B2
公开(公告)日：2016-06-07
申请号：US13411444
申请日：2012-03-02
申请人： Prasad Srinivasa Siva Gudem , Gurkanwal Singh Sahota , Li-chung Chang , Christian Holenstein , Frederic Bossu
发明人： Prasad Srinivasa Siva Gudem , Gurkanwal Singh Sahota , Li-chung Chang , Christian Holenstein , Frederic Bossu
IPC分类号： H04B1/00 , H04B7/04
CPC分类号： H04B1/0057 , H04B7/04
摘要： A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.
摘要翻译：描述了被配置为接收多载波信号的无线通信设备。无线通信设备包括单芯片信号分离载波聚合接收机架构。单芯片信号分离载波聚合接收机架构包括主天线，辅助天线和收发芯片。单芯片信号分离载波聚合接收机架构重用同步混合双接收机路径。

6. 发明授权

US08929840B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08929840B2
公开(公告)日：2015-01-06
申请号：US12209164
申请日：2008-09-11
申请人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/02 , H04B1/06 , H04B7/00 , H04B1/26 , H03D7/16 , H03D7/14 , H03G3/30
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

7. 发明申请

US20090111414A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 有权
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：US20090111414A1
公开(公告)日：2009-04-30
申请号：US11955201
申请日：2007-12-12
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/16
CPC分类号： H03D7/1441 , H03D7/165 , H03D7/166 , H03D2200/0084 , H03D2200/009
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

8. 发明申请

US20130231064A1 SINGLE-CHIP SIGNAL SPLITTING CARRIER AGGREGATION RECEIVER ARCHITECTURE 有权
标题翻译：单芯片信号分离载波聚合接收机架构
公开(公告)号：US20130231064A1
公开(公告)日：2013-09-05
申请号：US13411444
申请日：2012-03-02
申请人： Prasad Srinivasa Siva Gudem , Gurkanwal Singh Sahota , Li-Chung Chang , Christian Holenstein , Frederic Bossu
发明人： Prasad Srinivasa Siva Gudem , Gurkanwal Singh Sahota , Li-Chung Chang , Christian Holenstein , Frederic Bossu
IPC分类号： H04B1/38
CPC分类号： H04B1/0057 , H04B7/04
摘要： A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.
摘要翻译：描述了被配置为接收多载波信号的无线通信设备。无线通信设备包括单芯片信号分离载波聚合接收机架构。单芯片信号分离载波聚合接收机架构包括主天线，辅助天线和收发芯片。单芯片信号分离载波聚合接收机架构重用同步混合双接收机路径。

9. 发明授权

US08639205B2 Reduced power-consumption receivers 失效
标题翻译：降低功耗的接收机
公开(公告)号：US08639205B2
公开(公告)日：2014-01-28
申请号：US12052657
申请日：2008-03-20
申请人： Junxiong Deng , Aristotele Hadjichristos , Aleksandar Tasic , Frederic Bossu
发明人： Junxiong Deng , Aristotele Hadjichristos , Aleksandar Tasic , Frederic Bossu
IPC分类号： H04B1/26
CPC分类号： H04W52/0206 , H03G3/20 , H04B1/16
摘要： An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.
摘要翻译：公开的示例性实施例包括具有多个输入引线的混合器; 耦合到混合器的第一输入引线的第一退化阻抗元件; 耦合到混合器的第二输入引线的第二退化阻抗元件; 以及本地振荡器（LO）系统，其包括多个占空比模式以产生混频器的LO信号，本地振荡器系统基于混频器的第一增益状态在第一占空比中工作，并且在第二占空比基于混频器的第二增益状态。

10. 发明授权

US08615205B2 I-Q mismatch calibration and method 失效
标题翻译： I-Q不匹配校准和方法
公开(公告)号：US08615205B2
公开(公告)日：2013-12-24
申请号：US12259178
申请日：2008-10-27
申请人： Ojas M. Choksi , Frederic Bossu
发明人： Ojas M. Choksi , Frederic Bossu
IPC分类号： H03C1/62
CPC分类号： H04L5/1461 , H03D3/009 , H03M1/1019 , H03M1/66 , H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
摘要： Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.
摘要翻译：提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式