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1. 发明授权

US06624699B2 Current-controlled CMOS wideband data amplifier circuits 有权
公开(公告)号：US06624699B2
公开(公告)日：2003-09-23
申请号：US10028806
申请日：2001-10-25
申请人： Guangming Yin , Jun Cao
发明人： Guangming Yin , Jun Cao
IPC分类号： H03F345
CPC分类号： H03F1/14 , H03F1/483 , H03F2203/45018 , H03F2203/45512 , H03F2203/45554 , H03F2203/45714
摘要： Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

2. 发明授权

US08750338B2 Symmetrical clock distribution in multi-stage high speed data conversion circuits 有权
标题翻译：多级高速数据转换电路中的对称时钟分布
公开(公告)号：US08750338B2
公开(公告)日：2014-06-10
申请号：US13556863
申请日：2012-07-24
申请人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
发明人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
IPC分类号： H04J3/02
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0629 , H04L7/0008
摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).
摘要翻译：提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。时钟分配电路接收并对称地将时钟信号分配给数据转换电路。耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

3. 发明申请

US20120287950A1 SYMMETRICAL CLOCK DISTRIBUTION IN MULTI-STAGE HIGH SPEED DATA CONVERSION CIRCUITS 有权
标题翻译：多级高速数据转换电路中的对称时钟分配
公开(公告)号：US20120287950A1
公开(公告)日：2012-11-15
申请号：US13556863
申请日：2012-07-24
申请人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
发明人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
IPC分类号： H04J3/02
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0629 , H04L7/0008
摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).
摘要翻译：提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。时钟分配电路接收并对称地将时钟信号分配给数据转换电路。耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

4. 发明授权

US07778288B2 Symmetrical clock distribution in multi-stage high speed data conversion circuits 失效
标题翻译：多级高速数据转换电路中的对称时钟分布
公开(公告)号：US07778288B2
公开(公告)日：2010-08-17
申请号：US12014094
申请日：2008-01-15
申请人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
发明人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
IPC分类号： H04J3/02
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0629 , H04L7/0008
摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).
摘要翻译：提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。时钟分配电路接收并对称地将时钟信号分配给数据转换电路。耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

5. 发明申请

US20100054384A1 SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER 有权
标题翻译：信号延迟结构在高速位流解复用器
公开(公告)号：US20100054384A1
公开(公告)日：2010-03-04
申请号：US12613740
申请日：2009-11-06
申请人： Jun Cao , Guangming Yin
发明人： Jun Cao , Guangming Yin
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H03K5/135 , H04J3/0629 , H04L7/0008 , H04L25/14
摘要： A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.
摘要翻译：在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和所有数据信号。这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

6. 发明授权

US07109799B2 Current-controlled CMOS wideband data amplifier circuits 失效
公开(公告)号：US07109799B2
公开(公告)日：2006-09-19
申请号：US10618462
申请日：2003-07-11
申请人： Guangming Yin , Jun Cao
发明人： Guangming Yin , Jun Cao
IPC分类号： H03F3/45 , H03F1/14 , H03F3/04
CPC分类号： H03F1/14 , H03F1/483 , H03F2203/45018 , H03F2203/45512 , H03F2203/45554 , H03F2203/45714
摘要： Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

7. 发明申请

US20100306568A1 SYMMETRICAL CLOCK DISTRIBUTION IN MULTI-STAGE HIGH SPEED DATA CONVERSION CIRCUITS 有权
标题翻译：多级高速数据转换电路中的对称时钟分配
公开(公告)号：US20100306568A1
公开(公告)日：2010-12-02
申请号：US12857049
申请日：2010-08-16
申请人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
发明人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
IPC分类号： G06F1/04
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0629 , H04L7/0008
摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).
摘要翻译：提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。时钟分配电路接收并对称地将时钟信号分配给数据转换电路。耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

8. 发明授权

US08259762B2 Symmetrical clock distribution in multi-stage high speed data conversion circuits 有权
标题翻译：多级高速数据转换电路中的对称时钟分布
公开(公告)号：US08259762B2
公开(公告)日：2012-09-04
申请号：US12857049
申请日：2010-08-16
申请人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
发明人： Guangming Yin , Bo Zhang , Mohammad Nejad , Jun Cao
IPC分类号： H04J3/02
CPC分类号： H04J3/0685 , H04J3/04 , H04J3/0629 , H04L7/0008
摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).
摘要翻译：提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。时钟分配电路接收并对称地将时钟信号分配给数据转换电路。耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

9. 发明授权

US07864909B2 Signal delay structure in high speed bit stream demultiplexer 有权
标题翻译：高速位流解复用器中的信号延迟结构
公开(公告)号：US07864909B2
公开(公告)日：2011-01-04
申请号：US12613740
申请日：2009-11-06
申请人： Jun Cao , Guangming Yin
发明人： Jun Cao , Guangming Yin
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H03K5/135 , H04J3/0629 , H04L7/0008 , H04L25/14
摘要： A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.
摘要翻译：在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和所有数据信号。这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

10. 发明授权

US07616725B2 Signal delay structure in high speed bit stream demultiplexer 有权
标题翻译：高速位流解复用器中的信号延迟结构
公开(公告)号：US07616725B2
公开(公告)日：2009-11-10
申请号：US10445771
申请日：2003-05-27
申请人： Jun Cao , Guangming Yin
发明人： Jun Cao , Guangming Yin
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H03K5/135 , H04J3/0629 , H04L7/0008 , H04L25/14
摘要： A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.
摘要翻译：在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和所有数据信号。这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

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