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1. 发明申请

US20050076285A1 Error correction coding utilizing numerical base conversion for modulation coding 有权
标题翻译：利用数字转换进行调制编码的纠错编码
公开(公告)号：US20050076285A1
公开(公告)日：2005-04-07
申请号：US10184758
申请日：2002-06-27
申请人： Gregory Silvus , Kent Anderson
发明人： Gregory Silvus , Kent Anderson
IPC分类号： G11B20/14 , G11B20/18 , H03M5/14 , H03M13/15 , H03M13/00 , G11C29/00
CPC分类号： G11B20/1803 , G11B20/1426 , G11B2020/1457 , H03M5/145 , H03M13/1515
摘要： A method of encoding data includes representing the data as number(s) in a first base. The method further includes converting the number(s) into a number(s) in a second base. The resultant number in the second base can be viewed as data suitable for encoding using an ECC algorithm. After being ECC encoded, the data may be further modulation encoded. Modulation encoding may include transforming each symbol to a value that constrains run lengths of a binary value (e.g., zero). A decoding method and system checks a received data block for erroneous symbols, maps each received, encoded symbol to an associated ECC-encoded transform pair. The ECC encoded data may be decoded and corrected using the ECC and the locations of identified erroneous symbols. Finally, the corrected data sequence is converted from the second base back to the first base, from which the original data is retrieved.
摘要翻译：一种编码数据的方法包括将数据表示为第一基数中的数字。该方法还包括将数字转换为第二基数中的数字。第二基数中的结果数可被视为适合于使用ECC算法进行编码的数据。在被ECC编码之后，数据可以被进一步调制编码。调制编码可以包括将每个符号变换为约束二进制值（例如，零）的游程长度的值。解码方法和系统检查接收到的错误符号的数据块，将每个接收到的编码符号映射到相关联的ECC编码变换对。可以使用ECC和所识别的错误符号的位置对ECC编码数据进行解码和校正。最后，将校正后的数据序列从第二基底转换回第一个基底，从中恢复原始数据。

2. 发明申请

US20050138498A1 Channel processing data without leading sync mark 有权
标题翻译：通道处理数据，无前同步标记
公开(公告)号：US20050138498A1
公开(公告)日：2005-06-23
申请号：US10638910
申请日：2003-12-04
申请人： Gregory Silvus , Ewe Tan
发明人： Gregory Silvus , Ewe Tan
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11B20/10009 , G11B20/10527 , G11B2020/10759 , G11B2220/2516
摘要： An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.
摘要翻译：一种对准在通道输入处串行接收的数据位的装置和方法。包括第一数据位的多个数据位存储在具有大于数据位数的第一缓冲器位和缓冲器大小的缓冲器中。缓冲器中的数据位被移位以改善第一数据位和第一缓冲器位的对准。移位的数据位被测试进行对齐。如果数据位的测试表明正确对齐，则对齐的数据位从缓冲区发送到主机以供使用。如果数据位的测试指示未对准，则将数据位传递到错误处理过程。

3. 发明申请

US20050283702A1 Soft-decision decoding using selective bit flipping 有权
标题翻译：使用选择性位翻转的软判决解码
公开(公告)号：US20050283702A1
公开(公告)日：2005-12-22
申请号：US10869447
申请日：2004-06-16
申请人： Yingquan Wu , Gregory Silvus , Thomas Souvignier
发明人： Yingquan Wu , Gregory Silvus , Thomas Souvignier
IPC分类号： H03M13/00 , H03M13/15 , H03M13/45
CPC分类号： H03M13/455 , H03M13/1515 , H03M13/451
摘要： A method or apparatus that can form and test a data block variant by flipping a selected potentially bad bit that is consecutive with 1 or 2 sequences of several potentially good bits of a received block. The variant correctability test is optionally repeated several times before receiving another data block, in the event of ECC failures, each repetition using a different block variant.
摘要翻译：可以通过翻转与接收块的几个潜在好比特的1或2个序列连续的所选潜在坏位来形成和测试数据块变体的方法或装置。在接收另一个数据块之前可选地重复变型可校正性测试多次，在ECC故障的情况下，使用不同的块变体进行每次重复。

4. 发明申请

US20060282712A1 Low complexity pseudo-random interleaver 有权
标题翻译：低复杂度伪随机交织器
公开(公告)号：US20060282712A1
公开(公告)日：2006-12-14
申请号：US11131518
申请日：2005-05-18
申请人： Cenk Argon , Richard Born , Gregory Silvus , Thomas Souvignier , Peter Vasiliev
发明人： Cenk Argon , Richard Born , Gregory Silvus , Thomas Souvignier , Peter Vasiliev
IPC分类号： G06F11/00
CPC分类号： H03M13/276 , H03M13/2742
摘要： An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.
摘要翻译：交织器具有输入多路复用器，其在交织器输入处接收数据序列，并将数据序列分离成多个数据子块。交织器具有生成输入地址序列的线性反馈移位寄存器。交织器具有生成与每个数据子块相关联的输出地址序列的加法器电路。交织器具有将数据子块存储在由输入地址序列控制的地址处的存储器。存储器以由相关联的输出地址序列控制的交错序列再现每个数据子块。交织器具有输出多路复用器，其组合交错序列以提供交织器输出。

5. 发明申请

US20060265634A1 Iterative detector with ECC in channel domain 有权
公开(公告)号：US20060265634A1
公开(公告)日：2006-11-23
申请号：US11132414
申请日：2005-05-18
申请人： Gregory Silvus , Thomas Souvignier
发明人： Gregory Silvus , Thomas Souvignier
IPC分类号： H03M13/00
CPC分类号： H03M13/2966 , H03M13/2963 , H03M13/6331
摘要： A communications channel is provided, which includes a receive path having an iterative decoder and an ECC decoder. The iterative decoder has a soft channel detector with a soft output. The ECC decoder is coupled to decode bits produced from soft information received from the soft output and operates on the bits in a bit order that is the same as that on the soft output.

6. 发明申请

US20050283507A1 Selective sequence generation method and apparatus 有权
标题翻译：选择性序列生成方法和装置
公开(公告)号：US20050283507A1
公开(公告)日：2005-12-22
申请号：US10871453
申请日：2004-06-18
申请人： Thomas Souvignier , Purnima Naganathan , Gregory Silvus , Nan-Hsiung Yeh
发明人： Thomas Souvignier , Purnima Naganathan , Gregory Silvus , Nan-Hsiung Yeh
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/584 , G06F1/02 , G06F2207/582
摘要： A sequence generator is configured to be re-initialized to a value selected derived from a candidate group that is derived from a predetermined value. If and when the re-initializing is performed, it is fully performed within about one clock cycle of setting the sequence generator to the predetermined value. The sequence generator is optionally initialized by a local processor to which it is operatively coupled, after which the processor receives one sequence value each cycle.
摘要翻译：序列生成器被配置为被重新初始化为从从预定值导出的候选组导出的值。如果并且当进行重新初始化时，在将序列生成器设置为预定值的大约一个时钟周期内完全执行。序列发生器可选地由与其可操作地耦合的本地处理器初始化，之后处理器每个周期接收一个序列值。

7. 发明申请

US20050138522A1 Reverse error correction coding with run length limited constraint 有权
标题翻译：反向纠错编码，运行长度受限制
公开(公告)号：US20050138522A1
公开(公告)日：2005-06-23
申请号：US10719132
申请日：2003-11-21
申请人： Gregory Silvus
发明人： Gregory Silvus
IPC分类号： G06F11/00 , H03M5/14 , H03M13/00 , H03M13/31
CPC分类号： H03M5/145 , H03M13/31
摘要： A method and apparatus for communicating data is provided. The data is encoded in accordance with a run length limited (RLL) code. A seed is appended to the RLL encoded data. The seed can be used to alter the error correction code (ECC) parity to meet an RLL constraint.
摘要翻译：提供了一种用于传送数据的方法和装置。数据根据游程长度限制（RLL）代码进行编码。种子附加到RLL编码数据。种子可用于改变纠错码（ECC）奇偶校验以满足RLL约束。

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