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1. 发明授权

US6085277A Interrupt and message batching apparatus and method 失效
标题翻译：中断和消息批处理设备和方法
公开(公告)号：US6085277A
公开(公告)日：2000-07-04
申请号：US950755
申请日：1997-10-15
申请人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , William Joseph Armstrong , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , William Joseph Armstrong , Thomas Rembert Sand
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/546
摘要： An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.
摘要翻译：中断和消息批处理设备和方法通过将I / O完成事件与单个处理器中断分组，以使I / O操作等待时间要求与处理器利用率要求平衡来优化，从而减少处理器中断和结果上下文切换的数量和频率整体计算机系统性能。本发明在I / O总线上从处理器复合体向I / O适配器发送消息，命令连接到I / O适配器的I / O设备执行功能。完成命令功能后，I / O适配器中的消息处理器会生成一条消息，并将其发送到I / O总线上的处理器复合体。该消息在存储器的消息队列中排队，消息计数被更新，并且当消息计数超过消息步调计数时以及何时发送处理器复杂中断。如果消息具有相对较高的延迟，或者如果消息具有相对低的延迟，则信令定时器也可以被编程为具有快速的响应时间值。当消息排入队列时，启动信令定时器，然后当消息计数超过消息起搏计数或信令定时器过去时，信号通知处理器复杂中断。

2. 发明授权

US5983292A Message transport mechanisms and methods 失效
标题翻译：消息传输机制和方法
公开(公告)号：US5983292A
公开(公告)日：1999-11-09
申请号：US950593
申请日：1997-10-15
申请人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , Thomas Rembert Sand
IPC分类号： G06F13/12 , G06F13/10 , G06F13/14
CPC分类号： G06F13/126
摘要： An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.
摘要翻译：一个I / O系统，包括一个处理器复合体和通过I / O适配器和I / O总线连接到I / O适配器的系统主存储器。消息传送机制和方法将上游消息队列和下游消息队列存储在系统主存储器中。队列地址存储在系统主存储器和I / O适配器的指定寄存器中。 I / O适配器利用队列地址来管理下游命令消息的传输，并通过跨I / O总线的直接存储器访问将上行响应消息发送到系统主存储器。

3. 发明授权

US6073253A Enhanced reset and built-in self-test mechanisms for single function and multifunction input/output devices 失效
标题翻译：增强的复位和内置自检机构，用于单功能和多功能输入/输出设备
公开(公告)号：US6073253A
公开(公告)日：2000-06-06
申请号：US995075
申请日：1997-12-19
申请人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , Paul John Johnsen , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , Paul John Johnsen , Thomas Rembert Sand
IPC分类号： G06F1/24 , G06F11/267 , G06F11/00
CPC分类号： G06F11/267 , G06F1/24
摘要： An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state. Each of these reset states is well-defined and has the advantage of predictable behavior during and after execution of the corresponding reset procedure. A built-in self-test procedure is also defined that sequentially examines each function associated within a multifunction device connected to the local bus to coordinate the initiation, execution and completion of built in self-tests.
摘要翻译：允许各种复位过程和相应复位状态的装置，系统和方法。为单个功能或多功能设备中的每个I / O设备适配器提供器件复位控制寄存器。器件复位控制寄存器允许对单个功能器件，多功能器件作为一个整体进行更大程度的控制，以及多功能器件中的各个器件功能。设备立即状态寄存器可以同步各种复位过程。逻辑上电复位程序，有向单元复位程序和定向接口复位程序利用设备复位控制寄存器提供的更大程度的控制力将I / O设备适配器，单功能设备或多功能设备强制为相应的逻辑上电复位状态，定向单元复位状态或定向接口复位状态。这些复位状态中的每一个都被明确定义，并且具有在执行相应的复位过程期间和之后可预测的行为的优点。还定义了一个内置的自检程序，依次检查连接到本地总线的多功能设备中相关联的每个功能，以协调内置自检的启动，执行和完成。

4. 发明授权

US6023736A System for dynamically configuring I/O device adapters where a function configuration register contains ready/not ready flags corresponding to each I/O device adapter 失效
标题翻译：用于动态配置I / O设备适配器的系统，其中功能配置寄存器包含与每个I / O设备适配器对应的就绪/未就绪标志
公开(公告)号：US6023736A
公开(公告)日：2000-02-08
申请号：US995157
申请日：1997-12-19
申请人： Shawn Michael Lambeth , Charles Scott Graham , Daniel Frank Moertl , Paul Edward Movall , Gregory Michael Nordstrom
发明人： Shawn Michael Lambeth , Charles Scott Graham , Daniel Frank Moertl , Paul Edward Movall , Gregory Michael Nordstrom
IPC分类号： G06F13/10
CPC分类号： G06F13/102
摘要： An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.
摘要翻译：允许动态配置连接到总线的I / O设备适配器的设备，系统和方法利用功能配置寄存器来存储每个I / O设备适配器的READY / NOT READY状态。在发生复位条件时，动态配置决策逻辑检测哪个I / O设备适配器连接到总线，确定每个连接的I / O设备适配器的配置参数，初始化每个连接的I / O设备适配器的配置空间，然后在功能配置寄存器中设置相应的标志，以指示就绪状态。 I / O设备驱动程序中断配置过程以检查功能配置寄存器。如果可以在超时期内从该功能配置寄存器确认就绪状态，则可以进行配置处理; 否则，启动设备错误恢复过程。

5. 发明授权

US06233641B1 Apparatus and method of PCI routing in a bridge configuration 失效
标题翻译：在桥接配置中PCI路由的装置和方法允许独立使用总线
公开(公告)号：US06233641B1
公开(公告)日：2001-05-15
申请号：US09093441
申请日：1998-06-08
申请人： Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl , Paul Edward Movall
发明人： Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl , Paul Edward Movall
IPC分类号： G06F1338
CPC分类号： G06F13/4022 , G06F13/4045
摘要： A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.
摘要翻译： PCI扩展卡接口的主PCI总线和多个辅助PCI总线通过路由电路互连。路由电路通过将每个辅助PCI总线与地址范围相关联并将从主PCI总线接收的命令转发到辅助PCI总线映射，分别用作主PCI总线和每个辅助PCI总线之间的交换桥到包括命令地址的地址范围。此外，路由电路从辅助PCI总线转发用于主PCI总线的命令。此外，当从一个辅助PCI总线接收的命令用于另一个PCI总线时，路由电路直接在辅助PCI总线之间路由命令，而不使用主总线。因此，主PCI总线上的流量和延迟降低，效率提高。

6. 发明授权

US06219761B1 Load/store assist engine 失效
标题翻译：加载/存储辅助引擎
公开(公告)号：US06219761B1
公开(公告)日：2001-04-17
申请号：US09072740
申请日：1998-05-06
申请人： Paul Edward Movall , Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl
发明人： Paul Edward Movall , Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl
IPC分类号： G06F1328
CPC分类号： G06F13/126 , G06F9/3879
摘要： An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.
摘要翻译：输入/输出总线架构，包括：输入/输出总线; 连接到输入/输出总线的输入/输出设备; 连接到输入/输出总线的主处理器，用于执行与输入/输出设备相对应的设备驱动器，设备驱动器为输入/输出设备产生加载/存储命令; 以及负载/存储辅助引擎，其连接到输入/输出总线，并且独立于主处理器，用于根据来自设备驱动程序的加载/存储命令向/从输入/输出设备加载/存储数据。加载/存储辅助引擎将主处理器与与执行加载/存储命令相关联的延迟分离。设备驱动程序被重新分配给主处理器，而不是在主处理器外部的设备（例如输入/输出处理器）中找到。

7. 发明授权

US07076634B2 Address translation manager and method for a logically partitioned computer system 有权
标题翻译：用于逻辑分区计算机系统的地址转换管理器和方法
公开(公告)号：US07076634B2
公开(公告)日：2006-07-11
申请号：US10422214
申请日：2003-04-24
申请人： Shawn Michael Lambeth , Travis James Pizel , Thomas Rembert Sand
发明人： Shawn Michael Lambeth , Travis James Pizel , Thomas Rembert Sand
IPC分类号： G06F12/10
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1009 , G06F2212/206
摘要： An address translation manager creates a set of chained tables that may be allocated in non-contiguous physical memory, and that may be dynamically resized as needed. The chained tables comprise one or more tables that each correspond to a logical partition, with each table including a pointer to a table corresponding to a virtual connection in the logical partition. The chained tables are managed by the address translation manager, which uses the system memory manager to dynamically allocate and free memory for a chained table as needed.
摘要翻译：地址转换管理器创建可以在非连续物理内存中分配的一组链表，并且可以根据需要动态调整大小。链表包括一个或多个表，每个表对应于逻辑分区，每个表包括指向与逻辑分区中的虚拟连接相对应的表的指针。链接表由地址转换管理器管理，地址转换管理器使用系统内存管理器根据需要动态分配和释放链接表的内存。

8. 发明授权

US07028157B2 On-demand allocation of data structures to partitions 有权
标题翻译：按需分配数据结构到分区
公开(公告)号：US07028157B2
公开(公告)日：2006-04-11
申请号：US10422680
申请日：2003-04-24
申请人： Timothy Roy Block , Shawn Michael Lambeth , Thomas Rembert Sand
发明人： Timothy Roy Block , Shawn Michael Lambeth , Thomas Rembert Sand
IPC分类号： G06F12/00
CPC分类号： G06F9/5016 , G06F9/5077 , G06F9/546
摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment dynamically allocate and/or deallocate data structures on demand to respective partitions in a logically-partitioned electronic device. The data structures are associated with an adapter, and the partitions may use the data structures to access the adapter and, in an embodiment, to send and/or receive messages across a network.
摘要翻译：一种方法，装置，系统和信号承载介质，其在一个实施例中根据需要将数据结构动态地分配和/或释放到逻辑分隔的电子设备中的相应分区。数据结构与适配器相关联，并且分区可以使用数据结构来访问适配器，并且在一个实施例中，通过网络发送和/或接收消息。

9. 发明授权

US06665813B1 Method and apparatus for updateable flash memory design and recovery with minimal redundancy 失效
标题翻译：用于可更新闪存设计和恢复的方法和设备，具有最小的冗余
公开(公告)号：US06665813B1
公开(公告)日：2003-12-16
申请号：US09631719
申请日：2000-08-03
申请人： Stephanie Maria Forsman , Shawn Michael Lambeth , Chetan Mehta , Paul Edward Movall
发明人： Stephanie Maria Forsman , Shawn Michael Lambeth , Chetan Mehta , Paul Edward Movall
IPC分类号： H02H305
CPC分类号： G06F11/1004
摘要： A method and an apparatus is presented for updating flash memory that contains a write protected code, a first copy of rewritable recovery code, a second copy of rewritable recovery code, and a rewritable composite code. Each block of rewritable code contains a checksum code to detect if the block of code has been corrupted. If it is detected that the first copy of the recovery code is corrupted then the second copy of the recovery code is copied into the first copy of the recovery code. If it is detected the second copy of the recovery code is corrupted then the first copy of the recovery code is copied into the second copy of the recovery code. The recovery code is responsible for checking and updating the composite code. If it is detected the composite code is corrupted then a fresh copy of the composite code is obtained from a removable storage device or a network connection. The data processing system is booted by executing the write protected code, the first copy of the recovery code, and the composite code. There is a minimum of redundant code by only replicating two copies of the recovery code while, at the same time, guaranteeing both the integrity and the updateability of the flash memory.
摘要翻译：提出了一种用于更新包含写保护代码，可重写恢复代码的第一副本，可重写恢复代码的第二副本和可重写复合代码的闪存的方法和装置。每个可重写代码块包含一个校验和代码，用于检测代码块是否已损坏。如果检测到恢复代码的第一个副本已损坏，则恢复代码的第二个副本将被复制到恢复代码的第一个副本中。如果检测到恢复代码的第二个副本已损坏，则恢复代码的第一个副本将被复制到恢复代码的第二个副本中。恢复代码负责检查和更新复合代码。如果检测到复合代码已损坏，则从可移动存储设备或网络连接获得复合代码的新副本。数据处理系统通过执行写保护代码，恢复代码的第一个副本和复合代码来引导。只有复制两个副本的恢复代码，同时保证了闪存的完整性和可更新性，才有最少的冗余代码。

10. 发明授权

US06934936B2 Apparatus and method for adaptive address-based historical utilization recording 失效
标题翻译：基于自适应地址的历史利用记录的装置和方法
公开(公告)号：US06934936B2
公开(公告)日：2005-08-23
申请号：US09775119
申请日：2001-02-01
申请人： Jason Alan Clegg , Charles Scott Graham , Shawn Michael Lambeth , Gene Steven Van Grinsven
发明人： Jason Alan Clegg , Charles Scott Graham , Shawn Michael Lambeth , Gene Steven Van Grinsven
IPC分类号： G06F9/44 , G06F11/34
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/805 , G06F2201/835 , G06F2201/865
摘要： An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The method further includes the step of updating the timestamp with an elapsed segment execution time, wherein the updating step is conducted through a plurality of hardware based operations that are executed without firmware interaction.
摘要翻译：提供了一种在处理系统中记录片段执行时间的装置和方法。该方法包括记录对应于要执行的段的开始的时间戳的步骤，其中记录步骤通过固件操作进行。该方法还包括以经过的分段执行时间更新时间戳的步骤，其中更新步骤通过在没有固件交互的情况下执行的多个基于硬件的操作进行。

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