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1. 发明授权

US6011731A Cell plate regulator 失效
标题翻译：电池板调节器
公开(公告)号：US6011731A
公开(公告)日：2000-01-04
申请号：US259221
申请日：1999-03-01
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C7/00 , G11C29/02 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/56
CPC分类号： G11C29/026 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C11/401 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

2. 发明授权

US06778452B2 Circuit and method for voltage regulation in a semiconductor device 失效
公开(公告)号：US06778452B2
公开(公告)日：2004-08-17
申请号：US10608060
申请日：2003-06-27
申请人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

3. 发明授权

US06469944B2 Method of compensating for a defect within a semiconductor device 失效
标题翻译：补偿半导体器件内的缺陷的方法
公开(公告)号：US06469944B2
公开(公告)日：2002-10-22
申请号：US09735119
申请日：2000-12-11
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

4. 发明授权

US06445629B1 Method of stressing a memory device 有权
公开(公告)号：US06445629B1
公开(公告)日：2002-09-03
申请号：US09735330
申请日：2000-12-11
申请人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C700
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

5. 发明授权

US6028799A Memory circuit voltage regulator 失效
公开(公告)号：US6028799A
公开(公告)日：2000-02-22
申请号：US260232
申请日：1999-03-01
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C7/00 , G11C29/02 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/56 , G11C29/00
CPC分类号： G11C29/026 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C11/401 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

6. 发明授权

US5982687A Method of detecting leakage within a memory cell capacitor 有权
标题翻译：检测存储单元电容器内泄漏的方法
公开(公告)号：US5982687A
公开(公告)日：1999-11-09
申请号：US260236
申请日：1999-03-01
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C7/00 , G11C29/02 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/56
CPC分类号： G11C29/026 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C11/401 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

7. 发明授权

US06882587B2 Method of preparing to test a capacitor 失效
标题翻译：准备测试电容器的方法
公开(公告)号：US06882587B2
公开(公告)日：2005-04-19
申请号：US10883415
申请日：2004-06-30
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C7/00 , G11C29/02 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/56
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取多次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

8. 发明授权

US06452846B1 Driver circuit for a voltage-pulling device 失效
标题翻译：电压牵引装置的驱动电路
公开(公告)号：US06452846B1
公开(公告)日：2002-09-17
申请号：US09733434
申请日：2000-12-08
申请人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Douglas J. Cutter , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

9. 发明授权

US06418071B2 Method of testing a memory cell 失效
标题翻译：测试存储单元的方法
公开(公告)号：US06418071B2
公开(公告)日：2002-07-09
申请号：US09735329
申请日：2000-12-11
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

10. 发明授权

US06188622B1 Method of identifying a defect within a memory circuit 失效
标题翻译：识别存储器电路中的缺陷的方法
公开(公告)号：US06188622B1
公开(公告)日：2001-02-13
申请号：US09483264
申请日：2000-01-13
申请人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
发明人： Kurt D. Beigel , Manny K. Ma , Gordon D. Roberts , James E. Miller , Daryl L. Habersetzer , Jeffrey D. Bruce , Eric T. Stubbs
IPC分类号： G11C2900
CPC分类号： G11C29/026 , G11C11/401 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/12 , G11C29/44 , G11C29/48 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C2029/5004
摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.
摘要翻译：作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

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