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1. 发明授权

US07915709B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07915709B2
公开(公告)日：2011-03-29
申请号：US11658228
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
IPC分类号： H01L29/66 , H01L21/8222
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

2. 发明申请

US20090008630A1 TUNNELING TRANSISTOR WITH BARRIER 有权
标题翻译：具有障碍物的隧道式晶体管
公开(公告)号：US20090008630A1
公开(公告)日：2009-01-08
申请号：US12161571
申请日：2007-01-24
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal
IPC分类号： H01L29/06
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/47 , H01L29/66666 , H01L29/78 , H01L29/7827 , Y10S977/762 , Y10S977/938
摘要： The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.
摘要翻译：本发明提出了一种包括源极（24）和漏极（29）的晶体管（21）以及位于源极和漏极之间的阻挡区域（27）。通过半导体材料的本征或低掺杂区域（26,28）将势垒区域与源极和漏极分离。在屏障区域和本征或低掺杂区域的界面处形成势垒。栅电极（32）设置在势垒附近，使得可以通过向栅电极施加适当的电压来调制势垒的有效高度和/或宽度。

3. 发明授权

US07868424B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07868424B2
公开(公告)日：2011-01-11
申请号：US11658227
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Erwin Hijzen , Raymond Josephus Engelbart Hueting
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Erwin Hijzen , Raymond Josephus Engelbart Hueting
IPC分类号： H01L21/02
CPC分类号： H01L29/0821 , B82Y10/00 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/08 , H01L29/423 , H01L29/42304 , H01L29/66242 , H01L29/737 , H01L29/7378
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted. According to the invention the collector region (3) borders the surface of the semiconductor body (12), while the emitter region (1) is recessed in the semiconductor body (12), and the collector region (3) forms part of a mesa structure (6) formed at the surface of the semiconductor body (12). Such a device (10) has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector (3) comprises a nanowire (30) forming the mesa structure (6).
摘要翻译：本发明涉及一种具有衬底（11）和半导体本体（12）的半导体器件（10），该半导体器件包括分别具有发射极区，基极区和集电极区（1,2,3）的垂直双极晶体管，第一导电类型，与第一导电类型和第一导电类型相反的第二导电类型，其中集电极区域（3）包括与基极区域（2）接壤的第一子区域（3A）与第二子区域（3A）接合的第一子区域（3A）的区域（3B），其具有比第二子区域（3B）低的掺杂浓度，并且晶体管设置有与第一子区域横向相邻的栅电极（5） 3A），并且借助于此可以使第一子区域（3A）耗尽。根据本发明，集电极区域（3）与半导体本体（12）的表面相接触，而发射极区域（1）凹入半导体本体（12）中，并且集电极区域（3）形成台面的一部分结构（6）形成在半导体本体（12）的表面。这种装置（10）在高频和高电压下具有非常有利的特性，而且易于制造。在优选实施例中，收集器（3）包括形成台面结构（6）的纳米线（30）。

4. 发明申请

US20090200641A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090200641A1
公开(公告)日：2009-08-13
申请号：US11658228
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

5. 发明申请

US20080315361A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080315361A1
公开(公告)日：2008-12-25
申请号：US11658227
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Erwin Hijzen , Raymond Josephus Engelbart Hueting
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Erwin Hijzen , Raymond Josephus Engelbart Hueting
IPC分类号： H01L27/00 , H01L21/331
CPC分类号： H01L29/0821 , B82Y10/00 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/08 , H01L29/423 , H01L29/42304 , H01L29/66242 , H01L29/737 , H01L29/7378
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted. According to the invention the collector region (3) borders the surface of the semiconductor body (12), while the emitter region (1) is recessed in the semiconductor body (12), and the collector region (3) forms part of a mesa structure (6) formed at the surface of the semiconductor body (12). Such a device (10) has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector (3) comprises a nanowire (30) forming the mesa structure (6).
摘要翻译：本发明涉及一种具有衬底（11）和半导体本体（12）的半导体器件（10），该半导体器件包括分别具有发射极区，基极区和集电极区（1,2,3）的垂直双极晶体管，第一导电类型，与第一导电类型和第一导电类型相反的第二导电类型，其中集电极区域（3）包括与基极区域（2）接壤的第一子区域（3A）与第二子区域（3A）接合的第一子区域（3A）的区域（3B），其具有比第二子区域（3B）低的掺杂浓度，并且晶体管设置有与第一子区域横向相邻的栅电极（5） 3A），并且借助于此可以使第一子区域（3A）耗尽。根据本发明，集电极区域（3）与半导体本体（12）的表面相接触，而发射极区域（1）凹入半导体本体（12）中，并且集电极区域（3）形成台面的一部分结构（6）形成在半导体本体（12）的表面。这种装置（10）在高频和高电压下具有非常有利的特性，而且易于制造。在优选实施例中，收集器（3）包括形成台面结构（6）的纳米线（30）。

6. 发明授权

US07791108B2 Nanowire tunneling transistor 失效
标题翻译：纳米线隧道晶体管
公开(公告)号：US07791108B2
公开(公告)日：2010-09-07
申请号：US12161574
申请日：2007-01-24
申请人： Fred Hurkx , Prabhat Agarwal
发明人： Fred Hurkx , Prabhat Agarwal
IPC分类号： H01L21/336 , H01L21/8235
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66666 , H01L29/7827 , Y10S977/75 , Y10S977/813 , Y10S977/938
摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
摘要翻译：晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

7. 发明授权

US07538593B2 Circuit and method to convert a single ended signal to duplicated signals 有权
标题翻译：将单端信号转换为重复信号的电路和方法
公开(公告)号：US07538593B2
公开(公告)日：2009-05-26
申请号：US11710270
申请日：2007-02-23
申请人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
发明人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
IPC分类号： G06F1/04
CPC分类号： H03K5/151
摘要： A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.
摘要翻译：公开了将单端信号转换为差分信号的电路。该电路具有两条路径，其中两条路径中的每条路径包括多个级。两个路径中的每个路段的数量是相同的。两个路径的第一路径包括缓冲段和至少一个逆变器级。两路径的第二路径包括至少两个逆变器级。缓冲级具有与第二路径的第一反相器级的延迟匹配的延迟。缓冲级包括第一对晶体管，其包括第一类别的第一晶体管，其可操作地连接到第二类别的第一晶体管，其沟道连接串联连接。

8. 发明申请

US20090008631A1 NANOWIRE TUNNELING TRANSISTOR 失效
标题翻译： NANOWIRE隧道晶体管
公开(公告)号：US20090008631A1
公开(公告)日：2009-01-08
申请号：US12161574
申请日：2007-01-24
申请人： Godefridus Andrianus Maria Hurkx , Prabhat Agarwal
发明人： Godefridus Andrianus Maria Hurkx , Prabhat Agarwal
IPC分类号： H01L29/06
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66666 , H01L29/7827 , Y10S977/75 , Y10S977/813 , Y10S977/938
摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
摘要翻译：晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

9. 发明申请

US20090008566A1 GEIGER MODE AVALANCHE PHOTODIODE 有权
公开(公告)号：US20090008566A1
公开(公告)日：2009-01-08
申请号：US12162999
申请日：2007-01-17
申请人： Prabhat Agarwal , Jan Sonsky , Lasse Juhana Kauppinen
发明人： Prabhat Agarwal , Jan Sonsky , Lasse Juhana Kauppinen
IPC分类号： G01T1/24 , H01L31/107 , H01L31/18
CPC分类号： H01L27/14658 , H01L27/1464 , H01L27/14683 , H01L31/107
摘要： A avalanche mode photodiode array (102) is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (100). The photodiodes (100) include an electrically insulative layer (206), a depletion region (204), and first (208) and second (210) doped regions. An interconnection layer (212) includes electrodes (214, 216) which provides electrical connections to the photodiodes. The photodiode array (102) is carried by a handle wafer (217).
摘要翻译：使用绝缘体上硅晶片和衬底转移工艺制造雪崩模式光电二极管阵列（102）。阵列包括多个光电二极管（100）。光电二极管（100）包括电绝缘层（206），耗尽区（204）以及第一（208）和第二（210）掺杂区。互连层（212）包括提供到光电二极管的电连接的电极（214,216）。光电二极管阵列（102）由处理晶片（217）承载。

10. 发明申请

US20070262397A1 Nanoscale Fet 有权
标题翻译：纳米级食物
公开(公告)号：US20070262397A1
公开(公告)日：2007-11-15
申请号：US11632738
申请日：2005-07-12
申请人： Radu Surdeanu , Prabhat Agarwal , Abraham Balkenende , Erik Bakkers
发明人： Radu Surdeanu , Prabhat Agarwal , Abraham Balkenende , Erik Bakkers
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/76 , Y10S438/962 , Y10S977/762 , Y10S977/818 , Y10S977/938
摘要： A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.
摘要翻译：晶体管器件由具有源极区，漏极区和源极和漏极区之间的沟道区的连续线性纳米结构形成。源极（20）和漏极（26）区域由纳米线形成，沟道区域（24）呈纳米管形式。绝缘栅极（32）设置成邻近沟道区（24），用于控制源极和漏极区之间的沟道区。

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