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1. 发明授权

US09684591B2 Storage system and storage apparatus 有权
公开(公告)号：US09684591B2
公开(公告)日：2017-06-20
申请号：US13519721
申请日：2012-04-27
申请人： Go Uehara , Shigeo Homma , Yoshiyuki Noborikawa
发明人： Go Uehara , Shigeo Homma , Yoshiyuki Noborikawa
IPC分类号： G06F13/00 , G06F12/02 , G06F3/06 , G06F11/10
CPC分类号： G06F12/0246 , G06F3/0688 , G06F11/108 , G06F2211/1059
摘要： A storage system comprises a first controller and a plurality of storage devices. The plurality of storage devices configure RAID, each of which includes one or more non-volatile memory chips providing storage space where data from a host computer is stored, and a second controller coupled to the non-volatile memory chips. In case where the first controller receives an update request to update first data to second data from the host computer, the second controller in a first storage device of the storage devices is configured to store the second data in an area different from an area where the first data has been stored, in the storage space of the first storage device; generate information that relates the first data and the second data; and generate an intermediate parity based on the first and the second data.

2. 发明申请

US20130290629A1 STORAGE SYSTEM AND STORAGE APPARATUS 有权
公开(公告)号：US20130290629A1
公开(公告)日：2013-10-31
申请号：US13519721
申请日：2012-04-27
申请人： Go Uehara , Shigeo Honma , Yoshiyuki Noborikawa
发明人： Go Uehara , Shigeo Honma , Yoshiyuki Noborikawa
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F3/0688 , G06F11/108 , G06F2211/1059
摘要： A storage system comprises a first controller and a plurality of storage devices. The plurality of storage devices configure RAID, each of which includes one or more non-volatile memory chips providing storage space where data from a host computer is stored, and a second controller coupled to the non-volatile memory chips. In case where the first controller receives an update request to update first data to second data from the host computer, the second controller in a first storage device of the storage devices is configured to store the second data in an area different from an area where the first data has been stored, in the storage space of the first storage device; generate information that relates the first data and the second data; and generate an intermediate parity based on the first and the second data.

3. 发明授权

US08738866B2 Storage system and control method therefor 有权
标题翻译：存储系统及其控制方法
公开(公告)号：US08738866B2
公开(公告)日：2014-05-27
申请号：US13510492
申请日：2012-05-02
申请人： Koji Sonoda , Go Uehara
发明人： Koji Sonoda , Go Uehara
IPC分类号： G06F12/00 , G06F12/02 , G06F3/06
CPC分类号： G06F12/0238 , G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F3/0688 , Y02D10/154
摘要： A storage system comprises multiple memory packages and a storage controller. The multiple memory packages respectively comprise multiple nonvolatile semiconductor memory devices for storing data, and a memory controller for controlling the reading/writing of data from/to these multiple semiconductor memory devices, and the storage controller receives an I/O command issued from a host computer, creates, on the basis of the received I/O command, a first level command for controlling the multiple memory packages, and sends this first level command to the multiple memory packages. The memory controllers of the multiple memory packages create a second level command for the multiple nonvolatile semiconductor memory devices inside its own memory package, and estimate the power to be consumed in its own memory package. In a case where the estimated power consumption exceeds a preconfigured permissible power, suspends the execution of the received second level command.
摘要翻译：存储系统包括多个存储器包和存储控制器。多个存储器封装分别包括用于存储数据的多个非易失性半导体存储器件和用于控制对这些多个半导体存储器件的数据的读取/写入的存储器控制器，并且存储控制器接收从主机发出的I / O命令计算机，根据所接收的I / O命令创建用于控制多个存储器包的第一级命令，并将该第一级命令发送到多个存储器包。多个存储器封装的存储器控制器为其自己的存储器封装内的多个非易失性半导体存储器件创建第二级命令，并且估计在其自己的存储器封装中被消耗的功率。在估计功率消耗超过预先配置的允许功率的情况下，暂停所接收到的第二级别命令的执行。

4. 发明申请

US20130297856A1 STORAGE SYSTEM AND CONTROL METHOD THEREFOR 有权
标题翻译：存储系统及其控制方法
公开(公告)号：US20130297856A1
公开(公告)日：2013-11-07
申请号：US13510492
申请日：2012-05-02
申请人： Koji Sonoda , Go Uehara
发明人： Koji Sonoda , Go Uehara
IPC分类号： G06F12/02
CPC分类号： G06F12/0238 , G06F3/0613 , G06F3/0625 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F3/0688 , Y02D10/154
摘要： A storage system comprises multiple memory packages and a storage controller. The multiple memory packages respectively comprise multiple nonvolatile semiconductor memory devices for storing data, and a memory controller for controlling the reading/writing of data from/to these multiple semiconductor memory devices, and the storage controller receives an I/O command issued from a host computer, creates, on the basis of the received I/O command, a first level command for controlling the multiple memory packages, and sends this first level command to the multiple memory packages. The memory controllers of the multiple memory packages create a second level command for the multiple nonvolatile semiconductor memory devices inside its own memory package, and estimate the power to be consumed in its own memory package. In a case where the estimated power consumption exceeds a preconfigured permissible power, suspends the execution of the received second level command.
摘要翻译：存储系统包括多个存储器包和存储控制器。多个存储器封装分别包括用于存储数据的多个非易失性半导体存储器件和用于控制对这些多个半导体存储器件的数据的读取/写入的存储器控制器，并且存储控制器接收从主机发出的I / O命令计算机，根据所接收的I / O命令创建用于控制多个存储器包的第一级命令，并将该第一级命令发送到多个存储器包。多个存储器封装的存储器控制器为其自己的存储器封装内的多个非易失性半导体存储器件创建第二级命令，并且估计在其自己的存储器封装中被消耗的功率。在估计功率消耗超过预先配置的允许功率的情况下，暂停所接收到的第二级别命令的执行。

5. 发明申请

US20140089729A1 STORAGE SYSTEM AND STORAGE CONTROL METHOD 审中-公开
标题翻译：存储系统和存储控制方法
公开(公告)号：US20140089729A1
公开(公告)日：2014-03-27
申请号：US13643903
申请日：2012-09-24
申请人： Koji Sonoda , Go Uehara
发明人： Koji Sonoda , Go Uehara
IPC分类号： G06F11/20
CPC分类号： G06F11/2087 , G06F11/108 , G06F2211/103 , G06F2211/1088 , G06F2211/109
摘要： A storage system includes a plurality of nonvolatile memory devices that each includes a plurality of nonvolatile memory chips, and a storage controller configured to perform input and output of data to and from a RAID group comprised by storage areas of the plurality of nonvolatile memory devices. A nonvolatile memory device identifies a failure occurrence area that is a storage area in which a failure occurred in the plurality of nonvolatile memory chips, excludes the failure occurrence area from a storage area allocated to the RAID group, and transmits failure occurrence information that is information relating to the failure that has occurred in the nonvolatile memory device to the storage controller. When the failure occurrence information is received, the storage controller reconstructs data that had been stored in a storage area including at least the failure occurrence area of the nonvolatile memory device.
摘要翻译：存储系统包括多个非易失性存储器件，每个非易失性存储器件均包括多个非易失性存储器芯片，以及存储控制器，被配置为执行数据输入和输出到由多个非易失性存储器件的存储区域组成的RAID组。非易失性存储装置识别作为在多个非易失性存储器芯片中发生故障的存储区域的故障发生区域，从分配给RAID组的存储区域排除故障发生区域，并且发送作为信息的故障发生信息涉及在非易失性存储器件中发生到存储控制器的故障。当接收到故障发生信息时，存储控制器重建已经存储在至少包括非易失性存储器件的故障发生区域的存储区域中的数据。

6. 发明申请

US20120254513A1 STORAGE SYSTEM AND DATA CONTROL METHOD THEREFOR 有权
标题翻译：存储系统及其数据控制方法
公开(公告)号：US20120254513A1
公开(公告)日：2012-10-04
申请号：US13125618
申请日：2011-04-04
申请人： Go Uehara , Koji Sonoda , Junji Ogawa
发明人： Go Uehara , Koji Sonoda , Junji Ogawa
IPC分类号： G06F12/00
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0688 , G06F11/1044 , G06F11/108 , G06F12/0246 , G06F2211/1059 , G06F2212/7211
摘要： A storage system having multiple flash memory packages including flash memory chips and package controllers for controlling access to the flash memory chips is configured such that the package controller receives from a higher-level apparatus, which sends a write request, frequency prediction information that enables prediction of an update frequency with respect to data, which is to be a write target, and when writing data for which a write request has been issued from the higher-level apparatus, control is executed such that data, which is predicted to have a relatively high update frequency based on the frequency prediction information, is preferentially stored in a physical block with the large remaining number of erases in a flash memory chip of flash memory package of the package controller, or such that data, which is predicted to have a relatively low update frequency based on the frequency prediction information, is preferentially stored in a physical block with the small remaining number of erases in a flash memory chip of the flash memory package of the package controller.
摘要翻译：配置具有多个快闪存储器包的存储系统，包括用于控制对闪速存储器芯片的访问的闪速存储器芯片和封装控制器，使得封装控制器从发送写入请求的更高级别的装置接收能够预测的频率预测信息相对于作为写入目标的数据的更新频率，并且当写入从较高级别装置发出写请求的数据时，执行控制，使得预测相对于基于频率预测信息的高更新频率优先存储在具有大量剩余擦除次数的物理块中，所述剩余数量在封装控制器的闪速存储器包的闪速存储器芯片中，或者使得预测具有相对基于频率预测信息的低更新频率优先存储在具有小rema的物理块中在包装控制器的闪速存储器包的闪速存储器芯片中引入擦除次数。

7. 发明授权

US07953909B2 Storage system comprising power saving function 有权
标题翻译：存储系统包括省电功能
公开(公告)号：US07953909B2
公开(公告)日：2011-05-31
申请号：US12782736
申请日：2010-05-19
申请人： Yoshifumi Zimoto , Go Uehara , Kenji Muraoka , Masaaki Kobayashi
发明人： Yoshifumi Zimoto , Go Uehara , Kenji Muraoka , Masaaki Kobayashi
IPC分类号： G06F3/00
CPC分类号： G06F3/0665 , G06F3/0625 , G06F3/0634 , G06F3/0689 , Y02D10/154
摘要： A storage system constituted such that power saving to an administrator-desired storage device can be performed from a management device. That is, the storage system comprises a power-saving indication receiving section for receiving from a management console a power-saving indication specifying at least one storage device of a plurality of RAID groups, a plurality of logical units, and a plurality of physical storage devices; and a power-saving controller for saving on power to one or more physical storage devices corresponding to the storage device specified in this power-saving indication.
摘要翻译：一种存储系统，其构成为能够从管理装置执行对管理员期望的存储装置的省电。也就是说，存储系统包括省电指示接收部分，用于从管理控制台接收指定多个RAID组，多个逻辑单元和多个物理存储器中的至少一个存储设备的功率指示设备; 以及省电控制器，用于对与该省电指示中指定的存储装置相对应的一个或多个物理存储设备进行供电。

8. 发明授权

US08832371B2 Storage system with multiple flash memory packages and data control method therefor 有权
标题翻译：具有多个闪存包的存储系统及其数据控制方法
公开(公告)号：US08832371B2
公开(公告)日：2014-09-09
申请号：US13125618
申请日：2011-04-04
申请人： Go Uehara , Koji Sonoda , Junji Ogawa
发明人： Go Uehara , Koji Sonoda , Junji Ogawa
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F11/10 , G06F12/02 , G06F3/06
CPC分类号： G06F3/064 , G06F3/0616 , G06F3/0688 , G06F11/1044 , G06F11/108 , G06F12/0246 , G06F2211/1059 , G06F2212/7211
摘要： A storage system having multiple flash memory packages including flash memory chips and package controllers for controlling access to the flash memory chips is configured such that the package controller receives from a higher-level apparatus, which sends a write request, frequency prediction information that enables prediction of an update frequency with respect to data, which is to be a write target, and when writing data for which a write request has been issued from the higher-level apparatus, control is executed such that data, which is predicted to have a relatively high update frequency based on the frequency prediction information, is preferentially stored in a physical block with the large remaining number of erases in a flash memory chip of flash memory package of the package controller, or such that data, which is predicted to have a relatively low update frequency based on the frequency prediction information, is preferentially stored in a physical block with the small remaining number of erases in a flash memory chip of the flash memory package of the package controller.
摘要翻译：配置具有多个快闪存储器包的存储系统，包括用于控制对闪速存储器芯片的访问的闪速存储器芯片和封装控制器，使得封装控制器从发送写入请求的更高级别的装置接收能够预测的频率预测信息相对于作为写入目标的数据的更新频率，并且当写入从较高级别装置发出写请求的数据时，执行控制，使得预测相对于基于频率预测信息的高更新频率优先存储在具有大量剩余擦除次数的物理块中，所述剩余数量在封装控制器的闪速存储器包的闪速存储器芯片中，或者使得预测具有相对基于频率预测信息的低更新频率优先存储在具有小rema的物理块中在包装控制器的闪速存储器包的闪速存储器芯片中引入擦除次数。

9. 发明授权

US08219748B2 Storage system comprising both power saving and diagnostic functions 有权
标题翻译：存储系统包括省电和诊断功能
公开(公告)号：US08219748B2
公开(公告)日：2012-07-10
申请号：US11668750
申请日：2007-01-30
申请人： Go Uehara , Yoshifumi Zimoto , Kenji Muraoka , Masaaki Kobayashi
发明人： Go Uehara , Yoshifumi Zimoto , Kenji Muraoka , Masaaki Kobayashi
IPC分类号： G06F12/00
CPC分类号： G06F3/0625 , G06F1/3221 , G06F1/3268 , G06F3/0634 , G06F3/0689 , G06F11/1092 , G06F11/1658 , G06F11/2094 , G06F11/3419 , G06F11/3485 , G06F2201/86 , G06F2201/88 , Y02D10/154 , Y02D10/34 , Y02D50/20
摘要： The respective physical storage devices of a storage system are set to a power-saving state in which these respective physical storage devices are able to respond to a prescribed type of command. Then, a first prescribed type of command is sent to the respective physical storage devices that are in the power-saving state, and the results of this first prescribed type of command are checked.
摘要翻译：存储系统的各个物理存储设备被设置为这些各个物理存储设备能够响应规定类型的命令的省电状态。然后，将第一规定类型的命令发送到处于省电状态的各个物理存储装置，并且检查该第一规定类型的命令的结果。

10. 发明授权

US08949511B2 Nonvolatile semiconductor storage system 有权
标题翻译：非易失性半导体存储系统
公开(公告)号：US08949511B2
公开(公告)日：2015-02-03
申请号：US13379223
申请日：2011-09-30
申请人： Atsushi Ishikawa , Koji Sonoda , Go Uehara , Junji Ogawa , Hideyuki Koseki
发明人： Atsushi Ishikawa , Koji Sonoda , Go Uehara , Junji Ogawa , Hideyuki Koseki
IPC分类号： G06F12/02 , G06F13/16 , G06F3/06
CPC分类号： G06F3/0608 , G06F3/0626 , G06F3/0635 , G06F3/0647 , G06F3/0658 , G06F3/0685 , G06F3/0688 , G06F12/0246 , G06F13/16 , G06F13/1684 , G06F13/4022
摘要： A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.
摘要翻译：非易失性半导体存储系统具有多个非易失性半导体存储介质，具有耦合到多个非易失性半导体存储介质的介质接口组（一个或多个接口器件）和多个开关的控制电路。介质接口组和多个开关经由数据总线耦合，并且每个开关和两个或更多个非易失性芯片中的每一个经由数据总线耦合。该开关被配置为切换耦合到媒体接口组的数据总线与耦合到耦合到该开关的多个非易失性芯片中的任何一个的数据总线之间的耦合。控制电路将写目标数据分成多个数据元，通过控制多个开关切换耦合，并将多个数据元素分配发送到多个非易失性芯片。

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