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1. 发明授权

US4829473A Peripheral control circuitry for personal computer 失效
标题翻译：个人电脑外围控制电路
公开(公告)号：US4829473A
公开(公告)日：1989-05-09
申请号：US886614
申请日：1986-07-18
申请人： Glenn Keller , Jay G. Miner
发明人： Glenn Keller , Jay G. Miner
IPC分类号： G06F13/12 , G06F3/06 , G06F3/16 , G06F13/32 , G06F13/38
CPC分类号： G06F3/0601 , G06F13/32 , G06F13/38 , G06F3/162 , G06F2003/0692
摘要： A peripheral control circuit for a computer system. Independent control and interface circuits are provided for left and right audio channels, for a communications port, for storage media, and for joysticks or paddles. Control logic is provided for direct memory access to system memory and for interrupts to the processor by each of the peripherals. Sound data corresponding to a sound waveform during a particular time period is fetched using DMA or interrupts. Registers store data for selecting the output rate of the sound data, the length of the sound waveform, and the volume of the sound waveform. Four audio channels and two separate audio ports are provide.
摘要翻译：一种用于计算机系统的外围控制电路。独立的控制和接口电路用于左右音频通道，通信端口，存储介质以及操纵杆或拨片。提供控制逻辑用于对系统存储器的直接存储器访问以及每个外围设备对处理器的中断。使用DMA或中断获取在特定时间段期间对应于声音波形的声音数据。注册存储数据，用于选择声音数据的输出速率，声音波形的长度和声音波形的音量。提供四个音频通道和两个独立的音频端口。

2. 发明授权

US5594473A Personal computer apparatus for holding and modifying video output signals 失效
标题翻译：用于保存和修改视频输出信号的个人计算机装置
公开(公告)号：US5594473A
公开(公告)日：1997-01-14
申请号：US29306
申请日：1993-03-08
申请人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
发明人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
IPC分类号： A63F13/00 , G09G5/02 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/397 , G09G5/42 , G09G5/06
CPC分类号： G09G5/024 , A63F13/00 , G09G5/24 , G09G5/363 , G09G5/397 , A63F2300/203 , G09G5/022 , G09G5/346 , G09G5/39 , G09G5/42
摘要： A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transferer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
摘要翻译：使用位图显示存储器组织和位平面寻址为视频显示提供数据的计算机。提供了两个位平面背景和八个可重复使用且易于移动的精灵的独立控制。附加逻辑允许在每个位平面背景和精灵中的数据之间动态可控的对象间优先级和碰撞检测。协处理器为寄存器中的数据提供视频波束同步更改，为主处理器释放通用计算任务。提供块图像转发器以将大块中的数据从一个存储器位置快速复制到另一个存储器位置。在保持和修改模式下，颜色输出电路保持先前显示的像素的值，而位平面数据修改这些值，允许同时显示大量增加的颜色数量。

3. 发明授权

US4435779A Data processing system with programmable graphics generator 失效
标题翻译：数据处理系统与可编程图形发生器
公开(公告)号：US4435779A
公开(公告)日：1984-03-06
申请号：US271324
申请日：1981-06-08
申请人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
发明人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
IPC分类号： A63F13/00 , G06F3/033 , G06F3/048 , G06T15/00 , G09G5/02 , G09G5/42 , G06F3/153
CPC分类号： G06F3/04845 , A63F13/00 , G06T15/005 , G09G5/024 , G09G5/42 , A63F2300/203
摘要： A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
摘要翻译：包括微处理器，存储器单元和显示单元的基于微处理器的数据处理系统设置有可编程图形生成器，其响应于并且控制也存储的一组显示指令将图形信息从存储器单元传送到显示单元在内存单元中。图形生成器包括用于从存储器单元顺序访问显示指令的第一寻址单元; 控制单元，用于接收，存储和解码这样的指令，并响应于每条指令的二进制状态发出监控信号; 第二寻址单元，用于响应于来自控制单元的监控信号从存储器单元访问图形信息; 以及用于访问存储在存储器单元中的可移动对象图形的第三寻址单元。

4. 发明授权

US5103499A Beam synchronized coprocessor 失效
标题翻译：光束同步共焦器
公开(公告)号：US5103499A
公开(公告)日：1992-04-07
申请号：US422022
申请日：1989-10-16
申请人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
发明人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
IPC分类号： A63F13/00 , G09G5/02 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/397 , G09G5/42
CPC分类号： G09G5/024 , A63F13/00 , G09G5/24 , G09G5/363 , G09G5/397 , A63F2300/203 , G09G5/022 , G09G5/346 , G09G5/39 , G09G5/42
摘要： A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transferer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
摘要翻译：使用位图显示存储器组织和位平面寻址为视频显示提供数据的计算机。提供了两个位平面背景和八个可重复使用且易于移动的精灵的独立控制。额外的逻辑允许在每个位平面背景和精灵中的数据之间动态可控的对象间优先级和碰撞检测。协处理器为寄存器中的数据提供视频波束同步更改，为主处理器释放通用计算任务。提供块图像转发器以将大块中的数据从一个存储器位置快速复制到另一个存储器位置。在保持和修改模式下，颜色输出电路保持先前显示的像素的值，而位平面数据修改这些值，允许同时显示大量增加的颜色数量。

5. 发明授权

US4777621A Video game and personal computer 失效
标题翻译：视频游戏和个人电脑
公开(公告)号：US4777621A
公开(公告)日：1988-10-11
申请号：US756910
申请日：1985-07-19
申请人： Jay G. Miner , Joseph C. Decuir , Ronald H. Nicholson
发明人： Jay G. Miner , Joseph C. Decuir , Ronald H. Nicholson
IPC分类号： G06F13/28 , G09G1/16 , G09G5/00 , G06F9/00
CPC分类号： G09G5/001 , G06F13/28 , G09G5/005 , G09G5/393 , G09G5/395 , G09G2360/126 , G09G2360/18
摘要： A video game home computer is implemented in NMOS (n type metal oxide semiconductor) technology with plural microprocessors. Centralized bus architecture and direct memory access (DMA) techniques are employed. A video display generator provides color signal outputs to drive a commercial television receiver display. This display generator receives inputs from both microprocessors and obtains data directly from memory. A bit map of display information is kept in memory, wherein bits of information in memory image the precise screen display for each instance in time. A bit map manipulator circuit performs, under microprocessor direction, logic function manipulation of the bit map data. Access between system components is accomplished via the bus architecture on a priority queue basis. Chip count and chip area is minimized.
摘要翻译：视频游戏家用计算机在具有多个微处理器的NMOS（n型金属氧化物半导体）技术中实现。采用集中式总线架构和直接存储器访问（DMA）技术。视频显示发生器提供彩色信号输出以驱动商业电视接收机显示。该显示生成器接收来自两个微处理器的输入并直接从存储器获取数据。显示信息的位图保存在存储器中，其中存储器中的信息位在时间上针对每个实例精确地显示屏幕。位图操纵器电路在微处理器方向下执行位图数据的逻辑功能操作。通过基于优先级队列的总线架构来实现系统组件之间的访问。芯片数量和芯片面积最小化。

6. 发明授权

US4471465A Video display system with multicolor graphics selection 失效
标题翻译：具有多色图形选择的视频显示系统
公开(公告)号：US4471465A
公开(公告)日：1984-09-11
申请号：US495314
申请日：1983-05-16
申请人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
发明人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
IPC分类号： A63F13/00 , G06F3/033 , G06F3/048 , G06T15/00 , G09G5/02 , G09G5/42 , G06F3/153
CPC分类号： G06F3/04845 , A63F13/00 , G06T15/005 , G09G5/024 , G09G5/42 , A63F2300/203
摘要： A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
摘要翻译：包括微处理器，存储器单元和显示单元的基于微处理器的数据处理系统设置有可编程图形生成器，其响应于并且控制也存储的一组显示指令将图形信息从存储器单元传送到显示单元在内存单元中。图形生成器包括用于从存储器单元顺序访问显示指令的第一寻址单元; 控制单元，用于接收，存储和解码这样的指令，并响应于每条指令的二进制状态发出监控信号; 第二寻址单元，用于响应于来自控制单元的监控信号从存储器单元访问图形信息; 以及用于访问存储在存储器单元中的可移动对象图形的第三寻址单元。

7. 发明授权

US4471464A Data processing system with programmable graphics generator 失效
公开(公告)号：US4471464A
公开(公告)日：1984-09-11
申请号：US489961
申请日：1983-04-29
申请人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
发明人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
IPC分类号： A63F13/00 , G06F3/033 , G06F3/048 , G06T15/00 , G09G5/02 , G09G5/42 , G06F3/153
CPC分类号： G06F3/04845 , A63F13/00 , G06T15/005 , G09G5/024 , G09G5/42 , A63F2300/203
摘要： A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

8. 发明授权

US4874164A Personal computer apparatus for block transfer of bit-mapped image data 失效
标题翻译：用于块映射图像数据的块传送的个人计算机装置
公开(公告)号：US4874164A
公开(公告)日：1989-10-17
申请号：US886796
申请日：1986-07-18
申请人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
发明人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
IPC分类号： G06F3/153 , A63F13/00 , G09G5/00 , G09G5/02 , G09G5/24 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395
CPC分类号： G09G5/024 , A63F13/00 , A63F13/40 , G09G5/24 , G09G5/363 , G09G5/39 , A63F2300/203 , G09G2360/127 , G09G5/346
摘要： A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transfer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the value for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
摘要翻译：使用位图显示存储器组织和位平面寻址为视频显示提供数据的计算机。提供了两个位平面背景和八个可重复使用且易于移动的精灵的独立控制。额外的逻辑允许在每个位平面背景和精灵中的数据之间动态可控的对象间优先级和碰撞检测。协处理器为寄存器中的数据提供视频波束同步更改，为主处理器释放通用计算任务。提供块图像传输以将大块中的数据从一个存储器位置快速复制到另一个存储器位置。在保持和修改模式下，颜色输出电路保持先前显示的像素的值，而位平面数据修改这些值，允许同时显示大量增加的颜色数量。

9. 发明授权

US4471463A Data processing system with programmable graphics generator 失效
公开(公告)号：US4471463A
公开(公告)日：1984-09-11
申请号：US487677
申请日：1983-04-22
申请人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
发明人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
IPC分类号： A63F13/00 , G06F3/033 , G06F3/048 , G06T15/00 , G09G5/02 , G09G5/42 , G06F3/153
CPC分类号： G06F3/04845 , A63F13/00 , G06T15/005 , G09G5/024 , G09G5/42 , A63F2300/203
摘要： A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

10. 发明授权

US4296476A Data processing system with programmable graphics generator 失效
标题翻译：具有可编程图形发生器的数据处理系统
公开(公告)号：US4296476A
公开(公告)日：1981-10-20
申请号：US1497
申请日：1979-01-08
申请人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
发明人： Steven T. Mayer , Jay G. Miner , Douglas G. Neubauer , Joseph C. Decuir
IPC分类号： G06F3/153 , A63F13/00 , G06F3/033 , G06F3/048 , G06T11/00 , G06T15/00 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/24 , G09G5/32 , G09G5/36 , G09G5/38 , G09G5/40 , G09G5/42
CPC分类号： G06F3/04845 , A63F13/00 , G06T15/005 , G09G5/024 , G09G5/42 , A63F2300/203
摘要： A microprocessor based data processing system including a microprocessor, a memory unit, and display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
摘要翻译：包括微处理器，存储器单元和显示单元的基于微处理器的数据处理系统设置有可编程图形生成器，其响应于并且控制也存储在显示单元中的一组显示指令而将图形信息从存储器单元传送到显示单元存储单元。图形生成器包括用于从存储器单元顺序访问显示指令的第一寻址单元; 控制单元，用于接收，存储和解码这样的指令，并响应于每条指令的二进制状态发出监控信号; 第二寻址单元，用于响应于来自控制单元的监控信号从存储器单元访问图形信息; 以及用于访问存储在存储器单元中的可移动对象图形的第三寻址单元。

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