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    • 4. 发明授权
    • Flash memory cell arrays having dual control gates per memory cell charge storage element
    • 具有每个存储单元电荷存储元件的双控制栅极的闪存单元阵列
    • US08334180B2
    • 2012-12-18
    • US13204533
    • 2011-08-05
    • Eliyahou Harari
    • Eliyahou Harari
    • H01L21/336
    • H01L27/11521G11C16/0483H01L21/28273H01L27/115H01L27/11524H01L29/42348H01L29/66825H01L29/7881
    • A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
    • 闪存NAND型EEPROM系统,其具有诸如浮置栅极的电荷存储元件阵列中的各个,与至少两个控制栅极线电容耦合。 控制栅极线优选地位于与浮动栅极的侧壁耦合的浮动栅极之间。 结果,期望地增加存储单元耦合比。 通常将所选行的浮置栅极的相对侧上的两个控制栅极线升高到相同的电压,而与所选行的紧邻和相对侧的未选择的浮动栅极行耦合的第二控制栅极线保持为低。 控制栅极线也可以与衬底电容耦合,以选择性地提高其在所选浮栅的区域中的电压。 通过形成间隔物的蚀刻掩模,可以使浮栅的长度和控制栅极线的厚度小于工艺的最小分辨率元件。
    • 5. 发明授权
    • Methods of operating a dual decoder portable media device
    • 操作双解码器便携式媒体设备的方法
    • US08213519B2
    • 2012-07-03
    • US12120253
    • 2008-05-14
    • Moshe RainesEliyahou HarariRan Carmeli
    • Moshe RainesEliyahou HarariRan Carmeli
    • H04N7/24G06K9/32G06T1/20
    • H04N9/7921G06F1/3203G06F1/3293H04N5/775H04N5/907H04N9/8042H04N9/8047Y02D10/122
    • Methods of operating a portable media device 100 including two onboard hardware media decoders (124, 128) operative to decode a given digital content item 148 are disclosed. In some embodiments, one of the onboard hardware media decoders 128 has a relatively high power consumption and produces a relatively ‘high quality’ media signal, and the other of the onboard hardware media decoder 124 has a relatively low power consumption and produces a relatively ‘low quality’ media signal. In one non-limiting use case: (i) when no external power is available, the relatively ‘low power’ hardware media decoder 124 may generate a relatively ‘low quality’ media signal which is presented on an onboard display screen 140a and/or onboard speaker 140b; and (ii) when external power is available, the relatively ‘high power’ hardware media decoder 128 may generate a relatively ‘high quality’ media signal which is exported out of the portable media device 100 via one or more media ports, and presented on an external host presentation device 160 (for example, a large-screen television).
    • 公开了操作便携式媒体设备100的方法,该便携式媒体设备100包括可操作以解码给定数字内容项目148的两个板上硬件媒体解码器(124,128)。 在一些实施例中,车载硬件介质解码器128中的一个具有相对高的功率消耗并产生相对“高品质”的媒体信号,并且车载硬件媒体解码器124中的另一个具有相对低的功率消耗并产生相对“ 低品质“媒体信号。 在一个非限制性使用情况下:(i)当没有外部电源可用时,相对“低功率”硬件媒体解码器124可以产生呈现在车载显示屏140a上的相对“低质量”媒体信号和/或 车载扬声器140b; 和(ii)当外部电源可用时,相对“高功率”的硬件媒体解码器128可以产生相对“高品质”的媒体信号,其通过一个或多个媒体端口从便携式媒体设备100导出, 外部主机呈现装置160(例如,大屏幕电视)。
    • 7. 发明申请
    • Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element
    • 具有每个存储单元电荷存储元件的双控制门的闪存单元阵列
    • US20110287619A1
    • 2011-11-24
    • US13204533
    • 2011-08-05
    • Eliyahou Harari
    • Eliyahou Harari
    • H01L21/336
    • H01L27/11521G11C16/0483H01L21/28273H01L27/115H01L27/11524H01L29/42348H01L29/66825H01L29/7881
    • A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
    • 闪存NAND型EEPROM系统,其具有诸如浮置栅极的电荷存储元件阵列中的各个,与至少两个控制栅极线电容耦合。 控制栅极线优选地位于与浮动栅极的侧壁耦合的浮动栅极之间。 结果,期望地增加存储单元耦合比。 通常将所选行的浮置栅极的相对侧上的两个控制栅极线升高到相同的电压,而与所选行的紧邻和相对侧的未选择的浮动栅极行耦合的第二控制栅极线保持为低。 控制栅极线也可以与衬底电容耦合,以选择性地提高其在所选浮栅的区域中的电压。 通过形成间隔物的蚀刻掩模,可以使浮栅的长度和控制栅极线的厚度小于工艺的最小分辨率元件。