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1. 发明授权

US08514999B2 Floating-point event counters with automatic prescaling 有权
标题翻译：具有自动预分频功能的浮点事件计数器
公开(公告)号：US08514999B2
公开(公告)日：2013-08-20
申请号：US13312715
申请日：2011-12-06
申请人： Giles R. Frazier , Venkat R. Indukuru , Alexander E. Mericas , John F. Spannaus
发明人： Giles R. Frazier , Venkat R. Indukuru , Alexander E. Mericas , John F. Spannaus
IPC分类号： H03K23/00
CPC分类号： G06F11/2284 , G06F11/0724 , G06F11/076 , G06F11/3024 , G06F11/3058 , G06F11/3082 , G06F11/3409 , G06F11/348 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.
摘要翻译：电子设备中的特定事件的发生通过在每次发生特定事件的可变数量时增加事件计数器来计数，并且随着总计数增加而自动增加该变量数。每当计数尾数溢出时，可变数（预分频值）可根据可编程的计数器基数在几何上增加。事件计数器由此提供硬件实现的自动预分频，同时显着减少支持非常大的计数范围所需的接口位数，并在非常大的事件计数下保持高精度。

2. 发明授权

US09152426B2 Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register 有权
标题翻译：在异步事件时启动辅助线程，同时处理控制线程并更新状态寄存器中的运行状态
公开(公告)号：US09152426B2
公开(公告)日：2015-10-06
申请号：US13447961
申请日：2012-04-16
申请人： Giles R. Frazier , Venkat R. Indukuru
发明人： Giles R. Frazier , Venkat R. Indukuru
IPC分类号： G06F9/48 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/4812 , G06F9/4843
摘要： A method of data processing includes a processor of a data processing system executing a controlling thread of a program and detecting occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the controlling thread of the program, the processor initiates execution of an assist thread of the program such that the processor simultaneously executes the assist thread and controlling thread of the program.
摘要翻译：一种数据处理方法包括执行程序的控制线程的数据处理系统的处理器，并且在执行程序的控制线程期间检测特定的异步事件的发生。响应于在执行程序的控制线程期间发生特定的异步事件，处理器启动程序的辅助线程的执行，使得处理器同时执行辅助线程并控制程序的线程。

3. 发明申请

US20130151837A1 APPLICATION MANAGEMENT OF A PROCESSOR PERFORMANCE MONITOR 审中-公开
标题翻译：处理器性能监视器的应用管理
公开(公告)号：US20130151837A1
公开(公告)日：2013-06-13
申请号：US13315407
申请日：2011-12-09
申请人： Giles R. Frazier , Venkat R. Indukuru
发明人： Giles R. Frazier , Venkat R. Indukuru
IPC分类号： G06F9/00
CPC分类号： G06F9/542 , G06F9/4812 , G06F11/1438 , G06F11/3409 , G06F2209/481
摘要： A method, system or computer usable program product for an operating system (OS) enabling an application direct control of a performance monitoring unit (PMU) including enabling the PMU to notify the application when a PMU exception occurs without interrupting the OS by controllably encoding a redirect field in an OS accessible control register, and enabling the application to reinitialize the PMU after the PMU exception.
摘要翻译：一种用于操作系统（OS）的方法，系统或计算机可用程序产品，其能够直接控制性能监视单元（PMU），包括当PMU异常发生时使PMU通知应用程序，而不会通过可控编码来中断OS 重定向字段在OS可访问控制寄存器中，并使应用程序在PMU异常之后重新初始化PMU。

4. 发明申请

US20130142301A1 FLOATING-POINT EVENT COUNTERS WITH AUTOMATIC PRESCALING 有权
标题翻译：浮动点活动计数器具有自动预处理功能
公开(公告)号：US20130142301A1
公开(公告)日：2013-06-06
申请号：US13312715
申请日：2011-12-06
申请人： Giles R. Frazier , Venkat R. Indukuru , Alexander E. Mericas , John F. Spannaus
发明人： Giles R. Frazier , Venkat R. Indukuru , Alexander E. Mericas , John F. Spannaus
IPC分类号： H03K23/00
CPC分类号： G06F11/2284 , G06F11/0724 , G06F11/076 , G06F11/3024 , G06F11/3058 , G06F11/3082 , G06F11/3409 , G06F11/348 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Occurrences of a particular event in an electronic device are counted by incrementing an event counter each time a variable number of the particular events have occurred, and automatically increasing that variable number as the total count increases. The variable number (prescale value) can increase geometrically according to a programmable counter base each time the count mantissa overflows. The event counter thereby provides hardware-implemented automatic prescaling while significantly reducing the number of interface bits required to support very large count ranges, and retaining high accuracy at very large event counts.
摘要翻译：电子设备中的特定事件的发生通过在每次发生特定事件的可变数量时增加事件计数器来计数，并且随着总计数增加而自动增加该变量数。每当计数尾数溢出时，可变数（预分频值）可根据可编程的计数器基数在几何上增加。事件计数器由此提供硬件实现的自动预分频，同时显着减少支持非常大的计数范围所需的接口位数，并在非常大的事件计数下保持高精度。

5. 发明授权

US08667253B2 Initiating assist thread upon asynchronous event for processing simultaneously with controlling thread and updating its running status in status register 有权
标题翻译：在异步事件时启动辅助线程，同时处理控制线程并更新状态寄存器中的运行状态
公开(公告)号：US08667253B2
公开(公告)日：2014-03-04
申请号：US12849903
申请日：2010-08-04
申请人： Giles R. Frazier , Venkat R. Indukuru
发明人： Giles R. Frazier , Venkat R. Indukuru
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/4812 , G06F9/4843
摘要： A processor of a data processing system executes a controlling thread of a program and detects occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the controlling thread of the program, the processor initiates execution of an assist thread of the program such that the processor simultaneously executes the assist thread and controlling thread of the program.
摘要翻译：数据处理系统的处理器执行程序的控制线程，并且在执行程序的控制线程期间检测特定的异步事件的发生。响应于在执行程序的控制线程期间发生特定的异步事件，处理器启动程序的辅助线程的执行，使得处理器同时执行辅助线程并控制程序的线程。

6. 发明授权

US09372819B2 I/O device N—port ID virtualization 有权
标题翻译： I / O设备N端口ID虚拟化
公开(公告)号：US09372819B2
公开(公告)日：2016-06-21
申请号：US12181397
申请日：2008-07-29
申请人： Giles R. Frazier , Matthew J. Kalos
发明人： Giles R. Frazier , Matthew J. Kalos
IPC分类号： G06F3/00 , G06F13/38 , H04L12/927 , G06F13/42 , H04L12/931 , H04L29/08 , G06F9/50
CPC分类号： G06F13/387 , G06F9/5077 , G06F13/42 , H04L47/805 , H04L49/357 , H04L67/1097
摘要： An I/O device obtains multiple unique N_Port IDs (identifiers) for a NPIV N_Port ID Virtualization (NPIV) capable physical adapter. Fabric management routines are able to assign the multiple unique N_Port IDs to distinct fabric zones. LUNs (logical unit numbers) are able to be associated with the multiple unique N_Port IDs such the LUNs associated with unique N_Port ID do not exceed a limitation. The I/O device is able to associate different resources with different unique N_Port IDs to limit the scope of actions of one or more hosts. The I/O device is able to configure one or more LUNs by the multiple unique N_Port IDs to control access. Different unique N_Port IDs are able to be configured to have different quality of service attributes and/or different levels of security. The I/O device may include multiple independent logical partitions (LPARs) and assign each multiple unique N_Port IDs.
摘要翻译： I / O设备为具有NPIV N_Port ID虚拟化（NPIV）能力的物理适配器获取多个唯一的N_Port ID（标识符）。结构管理例程能够为不同的结构区域分配多个唯一的N_Port ID。 LUN（逻辑单元号）能够与多个唯一N_Port ID相关联，例如与唯一N_Port ID相关联的LUN不超过限制。 I / O设备能够将不同的资源与不同的唯一N_Port ID相关联，以限制一个或多个主机的操作范围。 I / O设备能够通过多个唯一的N_Port ID配置一个或多个LUN来控制访问。可以将不同的唯一N_Port ID配置为具有不同的服务质量属性和/或不同级别的安全性。 I / O设备可以包括多个独立的逻辑分区（LPAR），并且分配每个多个唯一的N_Port ID。

7. 发明授权

US09229716B2 Time-based task priority boost management using boost register values 有权
标题翻译：使用升压寄存器值的基于时间的任务优先级升级管理
公开(公告)号：US09229716B2
公开(公告)日：2016-01-05
申请号：US13323268
申请日：2011-12-12
申请人： Christopher Francois , Giles R. Frazier , Bruce G. Mealey , Suresh E. Warrier
发明人： Christopher Francois , Giles R. Frazier , Bruce G. Mealey , Suresh E. Warrier
IPC分类号： G06F9/30 , G06F9/48 , G06F9/46
CPC分类号： G06F9/3009 , G06F9/4881 , G06F2209/486
摘要： According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.
摘要翻译：根据本公开的一个方面，公开了一种用于任务优先级提升管理的方法和技术。该方法包括：响应于以用户模式执行的线程，提升线程的优先级的指令，访问升压寄存器，内核模式可访问的升压寄存器; 确定升压寄存器的值; 并且响应于确定升压寄存器保持非零值，提高线程的优先级。

8. 发明申请

US20130179886A1 PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE 审中-公开
标题翻译：提供具有硬件特征信息的逻辑分段反映处理器核心的独家使用
公开(公告)号：US20130179886A1
公开(公告)日：2013-07-11
申请号：US13452745
申请日：2012-04-20
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
摘要翻译：用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器信息。如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行物理寄存器包含信息。

9. 发明申请

US20130152098A1 TASK PRIORITY BOOST MANAGEMENT 有权
标题翻译：任务优先加强管理
公开(公告)号：US20130152098A1
公开(公告)日：2013-06-13
申请号：US13323268
申请日：2011-12-12
申请人： Christopher Francois , Giles R. Frazier , Bruce G. Mealey , Suresh E. Warrier
发明人： Christopher Francois , Giles R. Frazier , Bruce G. Mealey , Suresh E. Warrier
IPC分类号： G06F9/46
CPC分类号： G06F9/3009 , G06F9/4881 , G06F2209/486
摘要： According to one aspect of the present disclosure, a method and technique for task priority boost management is disclosed. The method includes: responsive to a thread executing in user mode an instruction to boost a priority of the thread, accessing a boost register, the boost register accessible in kernel mode; determining a value of the boost register; and responsive to determining that the boost register holds a non-zero value, boosting the priority of the thread.
摘要翻译：根据本公开的一个方面，公开了一种用于任务优先级提升管理的方法和技术。该方法包括：响应于以用户模式执行的线程，提升线程的优先级的指令，访问升压寄存器，内核模式可访问的升压寄存器; 确定升压寄存器的值; 并且响应于确定升压寄存器保持非零值，提高线程的优先级。

10. 发明申请

US20130086581A1 PRIVILEGE LEVEL AWARE PROCESSOR HARDWARE RESOURCE MANAGEMENT FACILITY 有权
标题翻译：特权级注意处理器硬件资源管理设施
公开(公告)号：US20130086581A1
公开(公告)日：2013-04-04
申请号：US13251879
申请日：2011-10-03
申请人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
发明人： Giles R. Frazier , Michael K. Gschwind , Naresh Nayar
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F9/462 , G06F9/5077 , G06F2009/45579
摘要： Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
摘要翻译：多个机器状态寄存器被包括在处理器核心中，以便区分应用程序，监督线程和管理程序之间的硬件设施的使用。当初始化分区时，所有的设备最初被管理程序禁用。当对残疾设施进行访问时，管理程序将收到访问哪个设施的指示，并在管理程序的机器状态寄存器中设置相应的硬件标志。当应用程序尝试访问禁用的设备时，管理操作系统映像的主管接收到哪个设备被访问的指示，并在主管机器状态寄存器中设置相应的硬件标志。多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态，并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。

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