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1. 发明授权

US07751402B2 Method and apparatus for gigabit packet assignment for multithreaded packet processing 有权
标题翻译：用于多线程数据包处理的千兆位数据包分配的方法和装置
公开(公告)号：US07751402B2
公开(公告)日：2010-07-06
申请号：US10684078
申请日：2003-10-10
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , Donald F. Hooper
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , Donald F. Hooper
IPC分类号： H04L12/56
CPC分类号： H04L49/351 , H04L49/102 , H04L49/352
摘要： A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.
摘要翻译：具有多个处理元件的网络处理器，每个处理元件支持多个同时进行的程序线程，可以访问接口中的共享资源。分组数据从段中的高速端口接收，并且每个段被分配给程序线程之一。每个分组可以被分配给单个程序线程，两个程序线程 - 一个用于头部段处理，另一个用于处理有效载荷段 - 或分组中的数据段的不同程序线程。准备就绪状态和序列号的专用输入提供了通过高速端口接收分组数据所需的辅助功能。专用输入用于逐个循环地监视来自高速端口的就绪标志。分配的线程使用序列号来维护分组中段的排序，以及命令将完整分组写入传送队列。

2. 发明申请

US20090307469A1 REGISTER SET USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 有权
标题翻译：多用途平行处理器结构中使用的寄存器
公开(公告)号：US20090307469A1
公开(公告)日：2009-12-10
申请号：US12477287
申请日：2009-06-03
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器维护执行线程。执行线程访问组织成每个线程相对可寻址的多个相对可寻址的寄存器窗口的寄存器集。

3. 发明授权

US06661794B1 Method and apparatus for gigabit packet assignment for multithreaded packet processing 有权
标题翻译：用于多线程数据包处理的千兆位数据包分配的方法和装置
公开(公告)号：US06661794B1
公开(公告)日：2003-12-09
申请号：US09474650
申请日：1999-12-29
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , Donald F. Hooper
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , Donald F. Hooper
IPC分类号： H04L1256
CPC分类号： H04L49/351 , H04L49/102 , H04L49/352
摘要： A network processor that has multiple processing elements, each processing element supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads, or a different program thread for segment of data in a packet. For the two program threads, one program thread can be used for header segment processing and the other program thread can be used for handling payload segment(s). Dedicated inputs for ready status and sequence numbers can provide assistance for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.
摘要翻译：具有多个处理元件的网络处理器，每个处理元件支持多个同时的程序线程，并且能够访问接口中的共享资源。分组数据从段中的高速端口接收，并且每个段被分配给程序线程之一。每个数据包可以分配给单个程序线程，两个程序线程，或者分组中的数据段的不同程序线程。对于两个程序线程，一个程序线程可用于头段处理，另一个程序线程可用于处理有效负载段。准备状态和序列号的专用输入可以帮助通过高速端口接收分组数据。专用输入用于逐个循环地监视来自高速端口的就绪标志。分配的线程使用序列号来维护分组中段的排序，以及命令将完整分组写入传送队列。

4. 发明授权

US07991983B2 Register set used in multithreaded parallel processor architecture 有权
标题翻译：在多线程并行处理器架构中使用的寄存器集
公开(公告)号：US07991983B2
公开(公告)日：2011-08-02
申请号：US12477287
申请日：2009-06-03
申请人： Gilbert Wolrich , Matthew J Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/46 , G06F15/16
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
摘要翻译：一种基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器维护执行线程。执行线程访问组织成每个线程相对可寻址的多个相对可寻址的寄存器窗口的寄存器集。

5. 发明授权

US07421572B1 Branch instruction for processor with branching dependent on a specified bit in a register 失效
标题翻译：处理器的分支指令，取决于寄存器中指定的位
公开(公告)号：US07421572B1
公开(公告)日：2008-09-02
申请号：US10069195
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/32
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.
摘要翻译：描述诸如并行硬件的多线程处理器（12）之类的处理器。处理器（12）可以执行作为分支指令的计算机指令，其使处理器中的指令序列在设置或清零的寄存器（80,78,76b）的任何指定位上分支，并且指定哪个位指定的寄存器用作分支控制位。

6. 发明授权

US07546444B1 Register set used in multithreaded parallel processor architecture 有权
标题翻译：在多线程并行处理器架构中使用的寄存器集
公开(公告)号：US07546444B1
公开(公告)日：2009-06-09
申请号：US10070091
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD—3 . . . THREAD—0). The processor maintains execution threads (THREAD—3 . . . THREAD—0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD—3 . . . THREAD—0).
摘要翻译：描述了基于并行硬件的多线程处理器。该处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文（THREAD-3，...，THREAD-0）的多个微启动器。处理器维护执行线程（THREAD-3 ... THREAD-0）访问组织成多个相对可寻址的寄存器窗口的寄存器集合，这些寄存器窗口相对于每个线程可访问（THREAD-3 ... THREAD-0）。

7. 发明授权

US07191321B2 Microengine for parallel processor architecture 有权
标题翻译：用于并行处理器架构的Microengine
公开(公告)号：US07191321B2
公开(公告)日：2007-03-13
申请号：US10643438
申请日：2003-08-19
申请人： Debra Bernstein , Donald F. Hooper , Matthew J. Adiletta , Gilbert Wolrich , William Wheeler
发明人： Debra Bernstein , Donald F. Hooper , Matthew J. Adiletta , Gilbert Wolrich , William Wheeler
IPC分类号： G06F9/38 , G06F9/48
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器参考是针对偶数存储体还是存储器的奇数存储器排序存储器引用，以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

8. 发明授权

US06668317B1 Microengine for parallel processor architecture 有权
标题翻译：用于并行处理器架构的Microengine
公开(公告)号：US06668317B1
公开(公告)日：2003-12-23
申请号：US09387046
申请日：1999-08-31
申请人： Debra Bernstein , Donald F. Hooper , Matthew J. Adiletta , Gilbert Wolrich , William Wheeler
发明人： Debra Bernstein , Donald F. Hooper , Matthew J. Adiletta , Gilbert Wolrich , William Wheeler
IPC分类号： G06F948
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

9. 发明授权

US07610451B2 Data transfer mechanism using unidirectional pull bus and push bus 有权
标题翻译：数据传输机制采用单向拉总线和推送总线
公开(公告)号：US07610451B2
公开(公告)日：2009-10-27
申请号：US10057738
申请日：2002-01-25
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/3824 , G06F9/3851
摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.
摘要翻译：一种用于在编程代理和存储器资源之间传送数据的方法。该方法包括在处理代理和存储器资源之间传送数据，指定存储器资源，用于经由具有仲裁使用推送总线的多个源的推送总线将数据推送到处理代理，以及指定用于接收的存储器资源来自处理代理的数据经由具有仲裁使用拉总线的多个目的地的拉总线。

10. 发明授权

US06895457B2 Bus interface with a first-in-first-out memory 失效
标题翻译：总线接口具有先进先出的存储器
公开(公告)号：US06895457B2
公开(公告)日：2005-05-17
申请号：US10664202
申请日：2003-09-16
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta
IPC分类号： G06F13/38 , G06F13/00 , G06F12/00
CPC分类号： G06F13/385 , Y10S370/912
摘要： A system includes a multithreaded processor. The multithreaded processor includes a plurality of microengines, a memory controller, a first bus interface and a second bus interface. The second bus interface includes a first-in-first-out memory with a plurality of elements to store packet data and packet status. The system also includes a system bus coupled to the first bus interface and a network bus coupled to the second bus interface.
摘要翻译：系统包括多线程处理器。多线程处理器包括多个微引线，存储器控制器，第一总线接口和第二总线接口。第二总线接口包括具有用于存储分组数据和分组状态的多个元素的先进先出存储器。该系统还包括耦合到第一总线接口的系统总线和耦合到第二总线接口的网络总线。

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