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1. 发明授权

US07124335B2 Apparatus and method for testing MEGACO protocol 失效
标题翻译：用于测试MEGACO协议的装置和方法
公开(公告)号：US07124335B2
公开(公告)日：2006-10-17
申请号：US10910759
申请日：2004-08-02
申请人： Gil Young Choi , Kyou Ho Lee , Dong Guk Je , Jaewoo Park
发明人： Gil Young Choi , Kyou Ho Lee , Dong Guk Je , Jaewoo Park
IPC分类号： G01R31/28
CPC分类号： H04L12/66
摘要： Provided are an apparatus and method for testing call processing performance and conformance of a media gateway controller and a media gateway with respect to a media gateway control (MEGACO) protocol. The method includes generating a predetermined scenario regarding a test of call processing performance of a media gateway controller or a media gateway; selecting a function of the media gateway controller or the media gateway and emulating virtual analog lines between the media gateway controller and the media gateway according to the scenario; and testing the call processing performance of the media gateway controller or the media gateway using the virtual analog lines and the selected media gateway controller or the media gateway. Accordingly, it is possible to effectively test the call processing performance of the media gateway controller or a media gateway without test equipment.
摘要翻译：提供了一种用于测试关于媒体网关控制（MEGACO）协议的媒体网关控制器和媒体网关的呼叫处理性能和一致性的装置和方法。该方法包括产生关于媒体网关控制器或媒体网关的呼叫处理性能测试的预定场景; 选择媒体网关控制器或媒体网关的功能，并根据场景模拟媒体网关控制器和媒体网关之间的虚拟模拟线路; 以及使用虚拟模拟线路和所选择的媒体网关控制器或媒体网关测试媒体网关控制器或媒体网关的呼叫处理性能。因此，无需测试设备即可有效地测试媒体网关控制器或媒体网关的呼叫处理性能。

2. 发明授权

US06421343B1 Asynchronous transfer mode host adapter apparatus with ability of shared media access 有权
标题翻译：具有共享媒体访问能力的异步传输模式主机适配器设备
公开(公告)号：US06421343B1
公开(公告)日：2002-07-16
申请号：US09137535
申请日：1998-08-21
申请人： Jong Arm Jun , Chan Kim , Yeong Ho Park , Ik Kyun Kim , Young Wook Cha , Kyou Ho Lee , Hyup Jong Kim , Jae Geun Kim
发明人： Jong Arm Jun , Chan Kim , Yeong Ho Park , Ik Kyun Kim , Young Wook Cha , Kyou Ho Lee , Hyup Jong Kim , Jae Geun Kim
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L2012/5612 , H04L2012/5616 , H04L2012/5653
摘要： An asynchronous transfer mode (ATM) host adapting apparatus comprising: a storage block for storing packet information, received cells, and parameters; an ATM network interface handling block for performing direct memory access of ATM cells and parameter stored therein, segmenting transmit packet information, reassembling received cells, transmitting and receiving the ATM cells to physical media cell received, and arbitrating in the direct memory access; and a secondary interface block for connecting the storage block to the ATM network interface handling block.
摘要翻译：一种异步传输模式（ATM）主机适配装置，包括：存储分组信息，接收的小区和参数的存储块; 用于执行ATM信元的直接存储器访问和存储在其中的参数的ATM网络接口处理块，分组发送分组信息，重新组合接收到的小区，向所接收的物理介质小区发送和接收ATM信元，并在直接存储器访问中进行仲裁; 以及用于将存储块连接到ATM网络接口处理块的辅助接口块。

3. 发明授权

US06275504B1 Direct memory read and cell transmission apparatus for ATM cell segmentation system 失效
标题翻译：用于ATM信元分段系统的直接存储器读取和信元传输装置
公开(公告)号：US06275504B1
公开(公告)日：2001-08-14
申请号：US09138329
申请日：1998-08-24
申请人： Chan Kim , Jong Arm Jun , Kyou Ho Lee , Hyup Jong Kim , Jae Geun Kim
发明人： Chan Kim , Jong Arm Jun , Kyou Ho Lee , Hyup Jong Kim , Jae Geun Kim
IPC分类号： H04J316
CPC分类号： H04Q11/0478 , H04L2012/5652 , H04L2012/5674
摘要： A direct memory read and cell transmission apparatus for an ATM cell segmentation system having a host CPU is disclosed. The segmentation circuit of the apparatus transfers the address and size for the start of the DMA by the byte unit. When a predetermined information is provided, and a DMA read is requested, the data is transferred through the bus of the word unit such as the PCI interface, and then necessary bytes are obtained for thereby forming a 32 bit word stream, so that the ATM cell of a 32 bit×12 word form and transfers to the lower circuit. Therefore, when the segmentation circuit processes the buffer, all data are computed by the byte unit, and in an application program, the data are not obtained for transmitting the data to the ATM cell, so that it is possible to enhance the processing capability.
摘要翻译：公开了一种具有主机CPU的ATM信元分段系统的直接存储器读和单元传输装置。该设备的分割电路通过字节单位传送DMA开始的地址和大小。当提供预定的信息并且请求DMA读取时，数据通过诸如PCI接口的字单元的总线传送，然后获得必要的字节，从而形成32位字流，使得ATM 32位x 12字形式的单元，并传输到较低电路。因此，当分割电路处理缓冲器时，所有数据都通过字节单位计算，并且在应用程序中，不能获得用于将数据发送到ATM信元的数据，从而可以提高处理能力。

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