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1. 发明申请

US20180033688A1 GAP-FILL POLYMER FOR FILLING FINE PATTERN GAPS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 有权
公开(公告)号：US20180033688A1
公开(公告)日：2018-02-01
申请号：US15470387
申请日：2017-03-27
申请人： Geun Su LEE , SK hynix Inc.
发明人： Ji Won MOON , Jin Wook JANG , Sang Youl YI , Sung Jae LEE , Geun Su LEE , Young Sun LEE , Min Su KIM
IPC分类号： H01L21/768 , H01L21/311 , C08G77/00 , C08G77/18 , C08G77/20 , H01L21/28 , H01L21/04
CPC分类号： H01L21/76861 , C08G77/18 , C08G77/20 , C08G77/80 , H01L21/048 , H01L21/28 , H01L21/311
摘要： A gap-fill polymer for filling fine pattern gaps, which has a low dielectric constant (flow-k) and excellent gap filling properties may consist of a compound formed by condensation polymerization of a first oligomer represented by the formula 1 and a second oligomer represented by the formula 2.

2. 发明申请

US20170372759A1 ACTIVE CONTROL CIRCUIT, INTERNAL VOLTAGE GENERATION CIRCUIT, MEMORY APPARATUS AND SYSTEM USING THE SAME 审中-公开
公开(公告)号：US20170372759A1
公开(公告)日：2017-12-28
申请号：US15279838
申请日：2016-09-29
申请人： SK hynix Inc.
发明人： Min Su KIM
IPC分类号： G11C7/22 , G11C5/14 , G11C8/18
CPC分类号： G11C7/22 , G11C5/147 , G11C5/148 , G11C8/18
摘要： A memory apparatus may include an active control circuit and an internal voltage generation circuit. The active signal generation circuit may enable an internal active signal after a level of a second external power supply voltage is stabilized even when a normal active signal is enabled. The internal voltage generation circuit may generate an internal voltage from a first external power supply voltage based on the internal active signal.

3. 发明申请

US20230024668A1 MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE 有权
公开(公告)号：US20230024668A1
公开(公告)日：2023-01-26
申请号：US17550234
申请日：2021-12-14
申请人： SK hynix Inc.
发明人： Won Jae CHOI , Min Su KIM , Hyun Chul CHO
IPC分类号： G11C16/32 , G11C16/30 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.

4. 发明公开

US20240007108A1 INPUT BUFFER CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 审中-公开
公开(公告)号：US20240007108A1
公开(公告)日：2024-01-04
申请号：US18107934
申请日：2023-02-09
申请人： SK hynix Inc.
发明人： In Seok KONG , Jae Hyeong HONG , Min Su KIM
IPC分类号： H03K19/0185 , H03K19/003
CPC分类号： H03K19/018521 , H03K19/00384
摘要： An input buffer circuit includes a signal input circuit and a linear setting circuit. The signal input circuit is configured to receive an input signal to generate an output signal based on a reference voltage and an activation current. The linear setting circuit is configured to compare a voltage of a first modeling node, which may correspond to the input signal, with a voltage of a second modeling node, which may correspond to the reference voltage, to generate a bias voltage for controlling the activation voltage.

5. 发明申请

US20200027510A1 MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 审中-公开
公开(公告)号：US20200027510A1
公开(公告)日：2020-01-23
申请号：US16299590
申请日：2019-03-12
申请人： SK hynix Inc.
发明人： Sang Hwan KIM , Min Su KIM , Kyeong Min CHAE
IPC分类号： G11C16/24 , G06F3/06
摘要： The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.

6. 发明申请

US20160071620A1 SEMICONDUCTOR MEMORY APPARATUS AND DATA PROCESSING SYSTEM WITH MAIN MEMORY BLOCKS AND REDUNDANT MEMORY BLOCKS SHARING A COMMON GLOBAL DATA LINE 有权
标题翻译：具有主存储块和冗余存储块的半导体存储器和数据处理系统共享通用全局数据线
公开(公告)号：US20160071620A1
公开(公告)日：2016-03-10
申请号：US14943252
申请日：2015-11-17
申请人： SK hynix Inc.
发明人： Min Su KIM
IPC分类号： G11C29/00 , G11C7/10
CPC分类号： G11C29/76 , G11C7/10 , G11C7/1069 , G11C8/00
摘要： A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.
摘要翻译：半导体存储装置包括：存储区域，包括多个存储器组，其具有分别通过多个全局数据线向外部发送数据和从外部接收数据的主存储区域以及被配置为使用的一个或多个冗余存储区域任何一个全球数据线作为一个共同的全球数据线; 以及被配置为控制通过公共全局数据线发送和接收的数据的控制器，作为冗余编程模式，冗余读取模式或冗余擦除模式。

7. 发明申请

US20150085590A1 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 有权
标题翻译：半导体器件和半导体系统，包括它们
公开(公告)号：US20150085590A1
公开(公告)日：2015-03-26
申请号：US14176837
申请日：2014-02-10
申请人： SK hynix Inc.
发明人： Min Su KIM
IPC分类号： G11C7/10 , G11C7/06
CPC分类号： G11C7/06 , G11C7/1048 , G11C2207/005
摘要： Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller is suitable for generating command signals and address signals. The semiconductor device is suitable for electrically disconnecting a first local line from a second local line in response to an input control signal enabled in a read mode. The read mode is set according to a logic combination of the command signals. Further, the semiconductor device is suitable for sensing and amplifying a data on the first local line or the second local line according to the address signals to output the amplified data through an input/output line.
摘要翻译：提供半导体系统。半导体系统包括控制器和半导体器件。控制器适用于产生指令信号和地址信号。半导体器件适于响应于在读取模式下启用的输入控制信号，将第一本地线路与第二本地线路电断开。读取模式根据命令信号的逻辑组合来设置。此外，半导体器件适用于根据地址信号来感测和放大第一本地线路或第二本地线路上的数据，以通过输入/输出线路输出放大的数据。

8. 发明公开

US20240007085A1 DUTY CYCLE CORRECTION CIRCUIT AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20240007085A1
公开(公告)日：2024-01-04
申请号：US18106915
申请日：2023-02-07
申请人： SK hynix Inc.
发明人： Dae Ho YANG , Min Su KIM , Kwan Su SHON , Keun Seon AHN , Soon Sung AN , Su Han LEE , Jae Hoon JUNG , Kyeong Min CHAE , Jae Hyeong HONG , Jun Sun HWANG
IPC分类号： H03K3/017 , H03K5/156 , H03K5/135 , H03K5/05
CPC分类号： H03K3/017 , H03K5/1565 , H03K5/135 , H03K5/05
摘要： A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

9. 发明公开

US20240007067A1 SIGNAL INPUT/OUTPUT CIRCUIT AND METHOD OF OPERATING THE SIGNAL INPUT/OUTPUT CIRCUIT 审中-公开
公开(公告)号：US20240007067A1
公开(公告)日：2024-01-04
申请号：US18111437
申请日：2023-02-17
申请人： SK hynix Inc.
发明人： In Seok KONG , Min Su KIM
IPC分类号： H03F3/45 , H03F1/26
CPC分类号： H03F3/45475 , H03F1/26
摘要： A signal input/output circuit includes a signal amplification circuit and a current control circuit. The signal amplification circuit configured to amplify and output an input signal transmitted through an input/output line. The current control circuit configured to induce a reverse virtual current corresponding to an output signal of the signal amplification circuit. The current control unit configured to reflect the reverse virtual current on the input/output line.

10. 发明申请

US20180041197A1 CURRENT BREAK CIRCUIT, SEMICONDUCTOR DEVICE HAVING THE SAME AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20180041197A1
公开(公告)日：2018-02-08
申请号：US15373738
申请日：2016-12-09
申请人： SK hynix Inc.
发明人： Min Su KIM , Kang Youl LEE
IPC分类号： H03K3/012 , H03K17/28 , H03K17/16
CPC分类号： H03K3/012 , H03K17/16 , H03K17/28 , H03K19/0016
摘要： A current break circuit includes a current break control circuit suitable for sequentially outputting a first enable signal and a second enable signal with a time difference in response to at least one control signal, and a current break switch circuit suitable for outputting or blocking a second voltage in response to a first voltage, wherein the current break switch circuit forms a first current path in response to the first enable signal and a second current path in response to the second enable signal when blocking the second voltage.

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