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1. 发明授权

US07404115B2 Self-synchronising bit error analyser and circuit 失效
标题翻译：自同步位误差分析器和电路
公开(公告)号：US07404115B2
公开(公告)日：2008-07-22
申请号：US11164690
申请日：2005-12-01
申请人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
发明人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
IPC分类号： G01R31/28
CPC分类号： G01R31/3171
摘要： A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
摘要翻译：一种自同步数据总线分析器，包括发生器LFSR，接收器LFSR和比较器，其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较，并且调整所述接收器LFSR，直到所述第二数据集与所述第一数据集基本相同。

2. 发明申请

US20070011534A1 SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT 失效
标题翻译：自同步位错误分析器和电路
公开(公告)号：US20070011534A1
公开(公告)日：2007-01-11
申请号：US11164690
申请日：2005-12-01
申请人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
发明人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
IPC分类号： G01R31/28
CPC分类号： G01R31/3171
摘要： A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
摘要翻译：一种自同步数据总线分析器，包括发生器LFSR，接收器LFSR和比较器，其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较，并且调整所述接收器LFSR，直到所述第二数据集与所述第一数据集基本相同。

3. 发明申请

US20090019326A1 Self-synchronizing bit error analyzer and circuit 失效
标题翻译：自同步位误差分析器和电路
公开(公告)号：US20090019326A1
公开(公告)日：2009-01-15
申请号：US12154188
申请日：2008-05-21
申请人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
发明人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
IPC分类号： G06F11/00
CPC分类号： G01R31/3171
摘要： A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
摘要翻译：提供了一种自同步数据总线分析器，其可以包括发生器线性反馈移位寄存器（LFSR）以产生第一数据集，并且可以包括接收器LFSR以生成第二数据集。数据总线分析器还可以包括比特采样器，以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样，并输出采样的第一数据集。可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较，并向接收机LFSR提供信号以调整接收机LFSR的相位，直到第二数据组与第一数据集基本相同数据集。

4. 发明授权

US07661039B2 Self-synchronizing bit error analyzer and circuit 失效
标题翻译：自同步位误差分析器和电路
公开(公告)号：US07661039B2
公开(公告)日：2010-02-09
申请号：US12154188
申请日：2008-05-21
申请人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
发明人： Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
IPC分类号： G06F11/00
CPC分类号： G01R31/3171
摘要： A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
摘要翻译：提供了一种自同步数据总线分析器，其可以包括发生器线性反馈移位寄存器（LFSR）以产生第一数据集，并且可以包括接收器LFSR以生成第二数据集。数据总线分析器还可以包括比特采样器，以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样，并输出采样的第一数据集。可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较，并向接收机LFSR提供信号以调整接收机LFSR的相位，直到第二数据组与第一数据集基本相同数据集。

5. 发明授权

US5621863A Neuron circuit 失效
标题翻译：神经元电路
公开(公告)号：US5621863A
公开(公告)日：1997-04-15
申请号：US481591
申请日：1995-06-07
申请人： Jean-Yves Boulet , Didier Louis , Catherine Godefroy , Andre Steimle , Pascal Tannhof , Guy Paillet
发明人： Jean-Yves Boulet , Didier Louis , Catherine Godefroy , Andre Steimle , Pascal Tannhof , Guy Paillet
IPC分类号： G06F15/18 , G06K9/66 , G06N3/00 , G06N3/06 , G06N3/063 , G06N3/08
CPC分类号： G06K9/6272 , G06K9/00986 , G06N3/063
摘要： In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.
摘要翻译：在由多个神经元电路组成的神经网络中，生成本地结果信号的改进的神经元电路，例如，的火灾类型，以及距离或类别类型的本地输出信号。连接到传送输入数据（例如输入类别）和控制信号的总线的神经元电路。多范围距离评估电路计算输入矢量和存储在R / W存储器电路中的原型矢量之间的距离D. 距离比较电路将该距离D与存储的原型矢量的实际影响场或其下限进行比较，以产生第一和第二比较信号。识别电路处理比较信号，输入类别信号，局部类别信号和反馈信号，以产生表示神经元电路对输入矢量的响应的本地结果信号。最小距离确定电路确定来自神经网络的所有神经元电路的所有计算距离中的最小距离Dmin，并产生距离类型的局部输出信号。该电路可用于搜索和分类。所有的神经元电路通过对所有的局部距离/类别进行OR运算来共同地产生反馈信号。菊花链电路串联连接到两个相邻神经元电路的相应菊花链电路，以将神经元链接在一起。菊花链电路还将神经元电路状态确定为自由或接合。最后，上下文电路在反馈信号的产生中实现或抑制与其他神经元电路的神经元参与。

6. 发明授权

US5463574A Apparatus for argument reduction in exponential computations of IEEE standard floating-point numbers 失效
标题翻译：用于IEEE标准浮点数的指数计算中的参数减少的装置
公开(公告)号：US5463574A
公开(公告)日：1995-10-31
申请号：US99119
申请日：1993-07-29
申请人： Bernard Desrosiers , Didier Louis , Didier Pinchon , Andre Steimle
发明人： Bernard Desrosiers , Didier Louis , Didier Pinchon , Andre Steimle
IPC分类号： G06F7/556 , G06F7/38
CPC分类号： G06F7/556 , G06F7/49947
摘要： An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.
摘要翻译：一种用于在F（x）= 2 ** x-1（具有| x | <1）的计算中执行参数减少的装置，根据IEEE 754标准浮点型确定xi的值和计算（x-xi）点格式具有第一电路装置，其可操作以对N位尾数执行流水线操作; 第一电路装置的输出连接到N + 4位的归一化电路，其三个最左边的输入被连接到“零”，并且其三个最左边的位J（0：2）位总线（J-BUS）。还包括一个领先的零检测器/编码器电路和第二电路装置，其可操作用于对输出控制对准器电路的编码器电路的指数执行流水线操作，以及由检测器/编码器电路和编码器电路的输出驱动的选择器电路其输出控制归一化电路; xi确定电路，其在连接到第一电路装置的xi-BUS上产生xi尾数，使得：尾数xi = 0 = K（1）K（2）1 0。。。，以及用于存储F（xi）值的只读存储器，其输出连接到用于F（xi）的相应尾数和指数部分的第一和第二电路的输入。

7. 发明授权

US06377941B1 Implementing automatic learning according to the K nearest neighbor mode in artificial neural networks 有权
标题翻译：根据人工神经网络中的K最近邻模式实现自动学习
公开(公告)号：US06377941B1
公开(公告)日：2002-04-23
申请号：US09338450
申请日：1999-06-22
申请人： Andre Steimle , Pascal Tannhof
发明人： Andre Steimle , Pascal Tannhof
IPC分类号： G06F1518
CPC分类号： G06K9/6271 , G06N3/063 , G06N3/08
摘要： A method of achieving automatic learning of an input vector presented to an artificial neural network (ANN) formed by a plurality of neurons, using the K nearest neighbor (KNN) mode. Upon providing an input vector to be learned to the ANN, a Write component operation is performed to store the input vector components in the first available free neuron of the ANN. Then, a Write category operation is performed by assigning a category defined by the user to the input vector. Next, a test is performed to determine whether this category matches the categories of the nearest prototypes, i.e. which are located at the minimum distance. If it matches, this first free neuron is not engaged. Otherwise, it is engaged by assigning the matching category to it. As a result, the input vector becomes the new prototype with the matching category associated thereto. Further described is a circuit which automatically retains the first free neuron of the ANN for learning.
摘要翻译：使用K个最近邻（KNN）模式，实现由多个神经元形成的人造神经网络（ANN）的输入向量的自动学习的方法。在向ANN提供要学习的输入向量时，执行写分量操作以将输入矢量分量存储在ANN的第一可用游离神经元中。然后，通过将由用户定义的类别分配给输入向量来执行写类别操作。接下来，执行测试以确定该类别是否与最近的原型的类别匹配，即位于最小距离的类别。如果它匹配，这个第一个自由神经元没有被使用。否则，通过将匹配类别分配给它来进行。结果，输入向量成为与其相关联的匹配类别的新原型。进一步描述了自动保留ANN的第一自由神经元进行学习的电路。

8. 发明授权

US5701397A Circuit for pre-charging a free neuron circuit 失效
标题翻译：为免费神经元电路预充电的电路
公开(公告)号：US5701397A
公开(公告)日：1997-12-23
申请号：US485336
申请日：1995-06-07
申请人： Andre Steimle , Didier Louis , Guy Paillet
发明人： Andre Steimle , Didier Louis , Guy Paillet
IPC分类号： G06F15/18 , G06N3/00 , G06N3/04 , G06N3/06 , G06N3/063
CPC分类号： G06K9/6271 , G06K9/00986 , G06N3/063
摘要： In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) for addressing the weight memory and a register (253) to latch the data output on the output data bus. After the determined neuron circuit has been engaged, the contents of its weight memory cannot be modified. Pre-charging the input vector during the recognition phase makes the engagement process more efficient and significantly reduces learning time in learning the input vector.
摘要翻译：在接合或自由状态下的多个神经元电路的神经网络中的每个神经元中，预充电电路允许在识别期间将输入矢量（A）的分量加载到确定的自由神经元电路中相作为附着到确定的神经元电路的潜在原型载体（B）。预充电电路是由存储器控制信号（RS）控制的重量存储器（251）和产生存储器控制信号的电路。存储器控制信号识别确定的自由神经元电路。在识别阶段期间，存储器控制信号仅对所确定的自由神经元电路有效。当神经网络是神经元电路链时，确定的游离神经元电路是链中的第一个游离神经元。输入数据总线（DATA-BUS）上的输入向量分量连接到所有神经元电路的权重存储器。其数据可在输出数据总线（RAM-BUS）上的每个神经元中使用。预充电电路还可以包括用于寻址权重存储器的地址计数器（252）和用于锁存输出数据总线上的数据的寄存器（253）。在确定的神经元电路被接合之后，其重量记忆的内容不能被修改。在识别阶段对输入向量进行预充电，使得参与过程更有效，并显着减少学习输入向量的学习时间。

9. 发明授权

US06502083B1 Neuron architecture having a dual structure and neural networks incorporating the same 失效
标题翻译：具有双重结构的神经元结构和包含其的神经网络
公开(公告)号：US06502083B1
公开(公告)日：2002-12-31
申请号：US09470458
申请日：1999-12-22
申请人： Didier Louis , Pascal Tannhof , Andre Steimle
发明人： Didier Louis , Pascal Tannhof , Andre Steimle
IPC分类号： G06N306
CPC分类号： G06K9/6276 , G06N3/063
摘要： The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other. The selection between the two modes (single/dual) is made by the user which stores a specific logic value in a dedicated register of the control logic circuitry in each improved neuron.
摘要翻译：改进的神经元连接到传输输入数据和控制信号的输入总线。它基本上由计算块，寄存器块，评估块和菊花链块组成。除了计算块之外，所有这些块基本上具有对称结构。寄存器用于存储数据：本地规范和上下文，距离，AIF值和类别。改进的神经元还需要一些R / W记忆容量，这可能被放置在神经元或外部。评估电路连接到输出总线，以在其上产生全局信号。菊花链块允许与其他人链接改进的神经元以形成人造神经网络（ANN）。改善的神经元可以作为单个神经元（单个模式）或两个独立的神经元（双模式）起作用。在后一种情况下，两个双重神经元共同的计算块必须依次操作，以便在一个神经元之后进行服务。两种模式之间的选择（单/双）由在每个改进的神经元中的控制逻辑电路的专用寄存器中存储特定逻辑值的用户进行。

10. 发明授权

US5452241A System for optimizing argument reduction 失效
标题翻译：用于优化参数减少的系统
公开(公告)号：US5452241A
公开(公告)日：1995-09-19
申请号：US209589
申请日：1994-03-14
申请人： Bernard Desrosiers , Louis Didier , Didier Pinchon , Andre Steimle
发明人： Bernard Desrosiers , Louis Didier , Didier Pinchon , Andre Steimle
IPC分类号： G06F7/38 , G06F7/483 , G06F7/487 , G06F7/52 , G06F7/527 , G06F7/533 , G06F7/548 , G06F17/10 , G06F7/00
CPC分类号： G06F7/4876 , G06F7/548 , G06F7/49942
摘要： A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.
摘要翻译：在数字处理系统中实现使用多项式扩展近似数学函数的方法。为了高精度降低参数大于pi / 4的多项式，提出了部分余数运算。该方法可以在具有所需结果的精度的大约一半宽度的总线的处理器中实现。临时寄存器用于存储中间结果。通过连续的半总线宽度操作获得完整的总线宽度精度。

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