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1. 发明授权

US5142731A Domestic electrical vacuum cleaner with suction tube holder 失效
标题翻译：家用电动真空清洁器，带吸管套管
公开(公告)号：US5142731A
公开(公告)日：1992-09-01
申请号：US565350
申请日：1990-08-10
申请人： Gerald Resch
发明人： Gerald Resch
IPC分类号： A47L9/00 , A47L9/24 , A47L9/28
CPC分类号： A47L9/0045
摘要： The invention relates to a vacuum cleaner with a suction tube nozzle unit, consisting of suction hose, handle, suction tube and suction nozzle, the suction nozzle unit being releasably connected to the vacuum cleaner housing by a coupling device.
摘要翻译：本发明涉及一种具有抽吸管喷嘴单元的真空吸尘器，其由抽吸软管，手柄，抽吸管和吸嘴组成，吸嘴单元通过联接装置可释放地连接到真空吸尘器外壳。

2. 发明授权

US5125127A Holding device on an electrical vacuum cleaner 失效
标题翻译：在电动真空清洁器上保持装置
公开(公告)号：US5125127A
公开(公告)日：1992-06-30
申请号：US609369
申请日：1990-11-05
申请人： Orest Bach , Gerald Resch
发明人： Orest Bach , Gerald Resch
IPC分类号： A47L5/36 , A47L9/00
CPC分类号： A47L9/0045
摘要： An electrical vacuum cleaner, including a vacuum cleaner housing, a suction tube nozzle unit, a suction hose, a suction tube and a suction nozzle, and a retaining arrangement for the suction tube nozzle unit which is provided on the vacuum cleaner housing, the retaining arrangement including a pivotable retaining clip for the suction tube and a retaining recess for a hook mounted on at least one of the suction tube and the suction nozzle, a spring arm movably mounted on an inner wall of the vacuum cleaner housing, the spring arm being hinged, at one end, to the retaining clip, its other end being operatively connectable to the hook in the region of the retaining recess, and a resiliently deformable holder mounted on the spring arm substantially at right angles to a direction of movement, the spring arm and the holder having a recoil force which is less than a force exerted by the hook on the spring arm.
摘要翻译：电动真空吸尘器，包括真空吸尘器外壳，吸管管嘴单元，抽吸软管，吸入管和吸嘴，以及设置在真空吸尘器外壳上的吸管管单元的保持装置，包括用于吸入管的可枢转保持夹和用于安装在吸入管和吸嘴中的至少一个上的钩的保持凹部，可移动地安装在真空吸尘器外壳的内壁上的弹簧臂，弹簧臂在一端铰接到保持夹上，其另一端在保持凹部的区域中可操作地连接到钩，以及可弹性变形的保持件，其基本上与运动方向成直角安装在弹簧臂上，弹簧臂和保持器具有小于由钩施加在弹簧臂上的力的反冲力。

3. 发明授权

US07251772B2 Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type 有权
标题翻译：在载体基板上具有多个集成电路部件的电路装置以及用于测试这种电路装置的方法
公开(公告)号：US07251772B2
公开(公告)日：2007-07-31
申请号：US10732402
申请日：2003-12-11
申请人： Christian Stocken , Gerald Resch , Manfred Pröll , Manfred Dobler
发明人： Christian Stocken , Gerald Resch , Manfred Pröll , Manfred Dobler
IPC分类号： G06F11/08 , G06F13/14
CPC分类号： G11C29/025 , G11C11/401 , G11C29/02 , G11C29/1201 , G11C2029/5006
摘要： A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.
摘要翻译：电路装置可以具有多个集成电路部件，其被布置在载体基板上。用于接收控制信号的接收电路可以耦合到输入侧的一个连接焊盘，并且可以连接到输出侧的每个电路部件。由测试模式信号控制的桥接电路可以使接收电路电桥。在测试方法中，多个连接焊盘可以连接到第一电位，并且至少一个连接焊盘可以连接到第二电位。可以激活桥接电路，并且通过测试装置在至少一个连接焊盘处测量电流。可以测量输入侧接收电路和电路部件之间的连接中的漏电流的检查。

4. 发明申请

US20050041519A1 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions 有权
标题翻译：用于存储器模块的集成时钟供应芯片，包括集成时钟供应芯片的存储器模块以及用于在测试条件下操作存储器模块的方法
公开(公告)号：US20050041519A1
公开(公告)日：2005-02-24
申请号：US10886523
申请日：2004-07-07
申请人： Nazif Taskin , Manfred Proll , Manfred Dobler , Gerald Resch
发明人： Nazif Taskin , Manfred Proll , Manfred Dobler , Gerald Resch
IPC分类号： G11C7/22 , G11C11/4076 , G11C29/14 , G11C8/18
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/14
摘要： The integrated chip according to the invention has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2-1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves for generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2-1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2-1.5).
摘要翻译：根据本发明的集成芯片具有用于施加第一时钟信号（clk1）和时钟信号输出（1.2-1.5）的时钟信号输入（1.1）。此外，它具有锁相环（2），其在输入侧连接到时钟信号输入端（1.1）并用于产生第二时钟信号（clk2）。此外，芯片具有多路复用器（MUX），第一时钟信号（clk1）或第二时钟信号（clk2）可以选择地切换到时钟信号输出（1.2-1.5），以及用于频率监视的单元 3），其在输入侧连接到时钟信号输入（1.1），并且被设计并且可以以这样的方式操作，使得在频率（fmin）不足的情况下，多路复用器（MUX ）将第一个时钟信号（clk1）切换到时钟信号输出（1.2-1.5）。

5. 发明授权

US07196554B2 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions 有权
标题翻译：用于存储器模块的集成时钟供应芯片，包括集成时钟供应芯片的存储器模块以及用于在测试条件下操作存储器模块的方法
公开(公告)号：US07196554B2
公开(公告)日：2007-03-27
申请号：US10886523
申请日：2004-07-07
申请人： Nazif Taskin , Manfred Pröll , Manfred Dobler , Gerald Resch
发明人： Nazif Taskin , Manfred Pröll , Manfred Dobler , Gerald Resch
IPC分类号： H03K17/00
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/14
摘要： An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves far generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2–1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2–1.5).
摘要翻译：集成芯片具有用于施加第一时钟信号（clk 1）和时钟信号输出（1.2-1.5）的时钟信号输入（1.1）。此外，它具有锁相环（2），其在输入侧连接到时钟信号输入（1.1）并且用于远远地产生第二时钟信号（clk 2）。此外，芯片具有多路复用器（MUX），第一时钟信号（clk 1）或第二时钟信号（clk 2）可以选择地切换到时钟信号输出（1.2-1.5），并且频率单位在输入侧连接到时钟信号输入（1.1）并且被设计并可以以这样的方式操作的监视（3），使得在频率（fmin）不足的情况下，多路复用器（MUX）将第一时钟信号（clk 1）切换到时钟信号输出（1.2-1.5）。

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