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1. 发明申请

US20150279444A1 APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：用于提供集成电路封装多个引脚的终止的装置，方法和系统
公开(公告)号：US20150279444A1
公开(公告)日：2015-10-01
申请号：US14440068
申请日：2013-11-22
申请人： George VERGIS , Kuljit S. BAINS , James A. MCCALL , Ge CHANG , INTEL CORPORATION
发明人： George Vergis , Kuljit S. Bains , James A. McCall , Ge Chang
IPC分类号： G11C11/4074 , G11C7/10 , G06F13/16 , G11C11/408
CPC分类号： G11C11/4074 , G06F3/0604 , G06F3/0637 , G06F3/0673 , G06F13/1663 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C7/109 , G11C8/06 , G11C11/408 , Y10T29/41
摘要： Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series
摘要翻译：用于为存储器件的多个芯片提供终端的技术和机制。在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

2. 发明授权

US09442871B2 Accessing data stored in a command/address register device 有权
标题翻译：访问存储在命令/地址寄存器中的数据
公开(公告)号：US09442871B2
公开(公告)日：2016-09-13
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F13/28 , G06F11/10 , G06F11/16 , G11C29/44 , G06F13/16
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

3. 发明申请

US20110252193A1 METHOD TO STAGGER SELF REFRESHES 有权
标题翻译：自动刷新的方法
公开(公告)号：US20110252193A1
公开(公告)日：2011-10-13
申请号：US12758667
申请日：2010-04-12
申请人： Kuljit S. Bains , George Vergis
发明人： Kuljit S. Bains , George Vergis
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C11/40611
摘要： A system, device, and method for designating a first rank among a plurality of memory ranks of a Memory Module as a primary rank and a second one or more ranks as secondary ranks, triggering, via hardware logic internal to the Memory Module coupled with the plurality of memory ranks, a refresh of the primary rank at a first time (e.g., Time1), and triggering a non overlapping staggered refresh of each of the secondary ranks at a second one or more times (e.g., Time2 through Timen) corresponding to each of the respective memory ranks designated as the secondary ranks.
摘要翻译：一种用于将作为主等级的存储器模块的多个存储器级别中的第一级指定为第二级别的第二级别的系统，设备和方法，并且经由与存储器模块耦合的存储器模块内部的硬件逻辑触发，多个存储器等级，第一次刷新主等级（例如，Time1），并且在第二次或更多次（例如，Time2至Timen）触发每个次级队列的非重叠交错刷新，对应于每个相应的记忆级别被指定为次级排名。

4. 发明申请

US20140372816A1 ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE 有权
标题翻译：访问存储在命令/地址寄存器设备中的数据
公开(公告)号：US20140372816A1
公开(公告)日：2014-12-18
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F11/10 , G06F11/16 , G11C29/44
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

5. 发明授权

US08649229B2 Memory module bus termination voltage (VTT) regulation and management 有权
标题翻译：内存模块总线终端电压（VTT）的调节和管理
公开(公告)号：US08649229B2
公开(公告)日：2014-02-11
申请号：US13172795
申请日：2011-06-29
申请人： George Vergis , Kuljit S. Bains
发明人： George Vergis , Kuljit S. Bains
IPC分类号： G11C5/14
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1063
摘要： Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了存储器模块总线终端电压（VTT）调节和管理技术和配置。一种方法包括通过寄存器将通过总线驱动的信号接收到包括多个存储器单元的存储器件，并且根据该信号在寄存器内设置总线的终端电压（VTT）。可以描述和/或要求保护其他实施例。

6. 发明申请

US20110246712A1 METHOD AND APPARATUS FOR INTERFACING WITH HETEROGENEOUS DUAL IN-LINE MEMORY MODULES 有权
标题翻译：用于连接异构双线内存模块的方法和装置
公开(公告)号：US20110246712A1
公开(公告)日：2011-10-06
申请号：US12753355
申请日：2010-04-02
申请人： George Vergis , Kuljit S. Bains , Joe Salmon
发明人： George Vergis , Kuljit S. Bains , Joe Salmon
IPC分类号： G06F12/00 , G11C29/00 , H03M13/00
CPC分类号： G06F13/1694
摘要： Described herein is a method and apparatus to interface a processor with a heterogeneous dual in-line memory module (DIMM). The method comprises determining an identity of a DIMM having data lanes; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes; and transferring data to and from the DIMM after training the I/O transceivers.
摘要翻译：这里描述的是将处理器与异构双列直插存储器模块（DIMM）进行接口的方法和装置。该方法包括确定具有数据通道的DIMM的身份; 基于确定DIMM的身份来映射数据通道; 训练输入输出（I / O）收发器以响应数据通道的映射; 并在训练I / O收发器之后向DIMM传输数据。

7. 发明授权

US07432731B2 Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations 有权
标题翻译：在过程，电压和温度（PVT）变化上校准DRAM电阻（Ron）和芯片上终端（ODT）值的方法和装置
公开(公告)号：US07432731B2
公开(公告)日：2008-10-07
申请号：US11174009
申请日：2005-06-30
申请人： Kuljit S. Bains , Navneet Dour , Hany Fahmy , George Vergis , Christopher E. Cox
发明人： Kuljit S. Bains , Navneet Dour , Hany Fahmy , George Vergis , Christopher E. Cox
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254 , H04L25/0298
摘要： An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.
摘要翻译：实施例可以包括具有存储器阵列的存储器，耦合到参考电压的电阻器，与电阻器耦合的管芯端接电路上，以及耦合到管芯端接电路并与存储器阵列耦合的输入端，用于接收校准命令停止使用输入和存储器阵列，并用耦合到参考电压的电阻校准芯片上的端接电路。本文公开了其它实施例。

8. 发明授权

US08484410B2 Method to stagger self refreshes 有权
标题翻译：错开自我刷新的方法
公开(公告)号：US08484410B2
公开(公告)日：2013-07-09
申请号：US12758667
申请日：2010-04-12
申请人： Kuljit S. Bains , George Vergis
发明人： Kuljit S. Bains , George Vergis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C11/406 , G11C11/40611
摘要： A system, device, and method for designating a first rank among a plurality of memory ranks of a Memory Module as a primary rank and a second one or more ranks as secondary ranks, triggering, via hardware logic internal to the Memory Module coupled with the plurality of memory ranks, a refresh of the primary rank at a first time (e.g., Time1), and triggering a non overlapping staggered refresh of each of the secondary ranks at a second one or more times (e.g., Time2 through Timen) corresponding to each of the respective memory ranks designated as the secondary ranks.
摘要翻译：一种用于将作为主等级的存储器模块的多个存储器级别中的第一级指定为第二级别的第二级别的系统，设备和方法，并且经由与存储器模块耦合的存储器模块内部的硬件逻辑触发，多个存储器等级，第一次刷新主等级（例如，Time1），并且在第二次或更多次（例如，Time2至Timen）触发每个次级队列的非重叠交错刷新，对应于每个相应的记忆级别被指定为次级排名。

9. 发明申请

US20140192607A1 ADAPTIVE VOLTAGE INPUT TO A CHARGE PUMP 有权
标题翻译：自适应电压输入到充电泵
公开(公告)号：US20140192607A1
公开(公告)日：2014-07-10
申请号：US13976791
申请日：2012-05-08
申请人： Kuljit Bains , George Vergis
发明人： Kuljit Bains , George Vergis
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C11/4074 , G11C29/021 , G11C29/028
摘要： A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification.
摘要翻译：存储器子系统包括自适应输出电压，以基于存储器子系统的存储器件的功率曲线来提供电压。电荷泵将电压提高到将数据写入存储器件所需的水平。所提供的电压基于存储器件的功率曲线，其指示为电荷泵提供良好效率的电压电平，并且在存储器件的最大电平内。电压可以高于规范中为存储器件指示的额定电压。

10. 发明申请

US20140013168A1 DELAY-COMPENSATED ERROR INDICATION SIGNAL 有权
标题翻译：延迟补偿错误指示信号
公开(公告)号：US20140013168A1
公开(公告)日：2014-01-09
申请号：US13997850
申请日：2012-03-31
申请人： Kuljit Singh Bains , George Vergis
发明人： Kuljit Singh Bains , George Vergis
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/108 , G11C5/04 , G11C7/1063 , G11C29/42 , G11C29/44 , G11C2029/0409 , G11C2029/0411
摘要： A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.
摘要翻译：存储器子系统具有耦合到命令/地址线和错误警报线的多个存储器件，误差警报线被延迟补偿以提供确定性警报信号定时。命令/地址线和错误警报线连接在存储器件和管理存储器件的存储器控制器之间。命令/地址线由存储器控制器驱动，错误警报线由存储器件驱动。

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