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1. 发明申请

US20100124813A1 Self-Aligned Three-Dimensional Non-Volatile Memory Fabrication 有权
标题翻译：自对准三维非易失性存储器制造
公开(公告)号：US20100124813A1
公开(公告)日：2010-05-20
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K. Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E. Scheuerlein
发明人： George Matamis , Henry Chien , James K. Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E. Scheuerlein
IPC分类号： H01L21/20 , H01L21/3205
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译：公开了一种用于三维非易失性存储器的自对准制造工艺。双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

2. 发明申请

US20100006812A1 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：基于碳的电阻率切换材料及其形成方法
公开(公告)号：US20100006812A1
公开(公告)日：2010-01-14
申请号：US12499467
申请日：2009-07-08
申请人： Huiwen Xu , Xiying Chen , Roy E. Scheuerlein , Er-Xuan Ping , Tanmay Kumar , Alper Ilkbahar
发明人： Huiwen Xu , Xiying Chen , Roy E. Scheuerlein , Er-Xuan Ping , Tanmay Kumar , Alper Ilkbahar
IPC分类号： H01L29/02 , H01L21/00
CPC分类号： B82Y10/00 , B82Y30/00 , C23C16/26 , G11C13/0014 , G11C13/025 , G11C2213/19 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/149 , H01L45/1616
摘要： Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.
摘要翻译：提供了包括碳基电阻率可切换材料的存储器件以及形成这种存储器件的方法，所述方法包括将处理气体引入处理室，其中所述处理气体包括烃化合物和载气，并且产生处理气体的等离子体，以将一层碳基可切换材料沉积在处理室内的基板上。还提供了许多其他方面。

3. 发明授权

US08309415B2 Methods and apparatus for increasing memory density using diode layer sharing 有权
标题翻译：使用二极管层共享增加存储密度的方法和装置
公开(公告)号：US08309415B2
公开(公告)日：2012-11-13
申请号：US12541078
申请日：2009-08-13
申请人： Huiwen Xu , Er-Xuan Ping , Roy E. Scheuerlein
发明人： Huiwen Xu , Er-Xuan Ping , Roy E. Scheuerlein
IPC分类号： H01L21/336
CPC分类号： H01L45/12 , H01L27/10 , H01L27/1021 , H01L27/1052 , H01L27/24 , H01L45/16
摘要： Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the memory element, but not the steering element, to form multiple memory cells that share a single steering element. Memory cells formed from such methods, as well as numerous other aspects are also disclosed.
摘要翻译：公开了形成存储器单元的方法，其包括在衬底上形成柱，所述柱包括操纵元件和存储元件，并且通过存储元件而不是导向元件垂直地执行一个或多个蚀刻，以形成多个存储单元共享一个转向元件。还公开了由这些方法形成的存储单元以及许多其它方面。

4. 发明申请

US20100038623A1 METHODS AND APPARATUS FOR INCREASING MEMORY DENSITY USING DIODE LAYER SHARING 有权
标题翻译：使用二极管共享增加记忆密度的方法和装置
公开(公告)号：US20100038623A1
公开(公告)日：2010-02-18
申请号：US12541078
申请日：2009-08-13
申请人： Huiwen Xu , Er-Xuan Ping , Roy E. Scheuerlein
发明人： Huiwen Xu , Er-Xuan Ping , Roy E. Scheuerlein
IPC分类号： H01L47/00 , H01L21/44
CPC分类号： H01L45/12 , H01L27/10 , H01L27/1021 , H01L27/1052 , H01L27/24 , H01L45/16
摘要： Methods of forming memory cells are disclosed which include forming a pillar above a substrate, the pillar including a steering element and a memory element, and performing one or more etches vertically through the memory element, but not the steering element, to form multiple memory cells that share a single steering element. Memory cells formed from such methods, as well as numerous other aspects are also disclosed.
摘要翻译：公开了形成存储器单元的方法，其包括在衬底上形成柱，所述柱包括操纵元件和存储元件，并且通过存储元件而不是导向元件垂直地执行一个或多个蚀刻，以形成多个存储单元共享一个转向元件。还公开了由这些方法形成的存储单元以及许多其它方面。

5. 发明申请

US20120127779A1 Re-writable Resistance-Switching Memory With Balanced Series Stack 有权
标题翻译：具有平衡串联堆叠的可重写电阻切换存储器
公开(公告)号：US20120127779A1
公开(公告)日：2012-05-24
申请号：US13363252
申请日：2012-01-31
申请人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
发明人： Roy E. Scheuerlein , Henry Chien , Zhida Lan , Yung-Tin Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/146 , G11C5/02 , G11C8/08 , G11C8/12 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/33 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a second bipolar resistance switching layer between third and fourth conductive layers. The first and third conductive layers are made of a common material, and the second and fourth conductive layers are made of a common material. In one approach, the first and second bipolar resistance switching layers are made of a common material and have common thickness. In another approach, the first and second bipolar resistance switching layers are made of materials having different dielectric constants, but their thickness differs in proportion to the difference in the dielectric constants, to provide a common capacitance per unit area.
摘要翻译：可重写电阻切换存储单元包括串联的第一和第二电容器。第一和第二电容器可以具有平衡的电气特性，以允许几乎同时进行相同方向的切换。第一电容器具有在第一和第二导电层之间的第一双极性电阻开关层，并且第二电容器在第三和第四导电层之间具有第二双极性电阻开关层。第一和第三导电层由普通材料制成，第二和第四导电层由普通材料制成。在一种方法中，第一和第二双极性电阻切换层由普通材料制成并且具有共同的厚度。在另一种方法中，第一和第二双极性电阻开关层由具有不同介电常数的材料制成，但它们的厚度与介电常数的差异成比例，以提供每单位面积的公共电容。

6. 发明授权

US08847200B2 Memory cell comprising a carbon nanotube fabric element and a steering element 有权
标题翻译：存储单元包括碳纳米管织物元件和转向元件
公开(公告)号：US08847200B2
公开(公告)日：2014-09-30
申请号：US13182960
申请日：2011-07-14
申请人： Scott Brad Herner , Roy E. Scheuerlein
发明人： Scott Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L29/06
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
摘要翻译：提供了一种存储单元，所述存储单元包括具有垂直取向的p-i-n结的转向元件和碳纳米管织物。导向元件和碳纳米管织物电串联布置，整个存储单元形成在基板上。还提供其他方面。

7. 发明授权

US08809128B2 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
标题翻译：用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化
公开(公告)号：US08809128B2
公开(公告)日：2014-08-19
申请号：US12911900
申请日：2010-10-26
申请人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
发明人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
IPC分类号： H01L21/82 , H01L27/24
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。公开了许多附加方面。

8. 发明授权

US08766332B2 Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
标题翻译：优化衬底中和图案上的图案特征的临界尺寸和间距
公开(公告)号：US08766332B2
公开(公告)日：2014-07-01
申请号：US13613956
申请日：2012-09-13
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L29/80
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

9. 发明授权

US08605486B2 Cross point non-volatile memory cell 有权
标题翻译：交叉点非易失性存储单元
公开(公告)号：US08605486B2
公开(公告)日：2013-12-10
申请号：US13591097
申请日：2012-08-21
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type.
摘要翻译：存储系统包括X线，第一Y线，第二Y线，沿着X线延伸的第一类型的半导体区域，第一开关材料和第一Y线与第一Y线之间的第二类型的第一半导体区域第一类型的半导体区域，第二开关材料和第二类型的第二类型的第二半导体区域在第二Y线和第一类型的半导体区域之间，以及控制电路。控制电路通过使第一电流从第二Y线流过第一Y线，通过第一开关材料，第二开关材料，第一开关材料的半导体区域，将第一开关材料的编程状态改变到第一状态第二类型的第一半导体区域和第二类型的第二半导体区域。

10. 发明授权

US08536015B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08536015B2
公开(公告)日：2013-09-17
申请号：US13351468
申请日：2012-01-17
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
IPC分类号： H01L21/00 , H01L21/06 , H01L29/02 , G11C11/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了形成金属 - 绝缘体 - 金属叠层的方法。该方法包括形成第一导电层，在第一导电层上形成电阻率切换碳基材料，并在碳基材料上形成第二导电层，其中碳基材料的厚度不大于十个原子层。还描述了其他方面。

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