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1. 发明授权

US4916692A TDM bus controller 失效
标题翻译： TDM总线控制器
公开(公告)号：US4916692A
公开(公告)日：1990-04-10
申请号：US167816
申请日：1988-03-14
申请人： George A. Clarke , Juan E. Farias , Raul F. Fernandez , Dale R. Jenkins , Jon S. Miller , Edward J. Sackman, III , Donald L. Wray , Leroy D. Young
发明人： George A. Clarke , Juan E. Farias , Raul F. Fernandez , Dale R. Jenkins , Jon S. Miller , Edward J. Sackman, III , Donald L. Wray , Leroy D. Young
IPC分类号： H04L12/403 , H04Q11/04
CPC分类号： H04L12/40013 , H04Q11/04
摘要： An apparatus for controlling access to a time division multiplexed (TDM) bus includes a frame address register having a plurality of storage registers for storing a plurality of frame addresses designated for use in communicating over said TDM bus. A frame address latch stores a current frame address. A frame comparator, coupled to the frame address register and the frame address latch, compares the designated frame addresses with the current frame address and produces a first signal indicative of the storage register containing a frame address matching the current frame address. A time slot register has a plurality of storage registers for storing a time slot number designated for use in communicating over said TDM bus. A time slot generator generates a current time slot number. A time slot comparator, coupled to the time slot register and the time slot generator compares the designated time slot number with the current time slot number and produces a second signal indicative of the storage register containing a slot number matching the current time slot number. A token generator, coupled to the frame comparator and the time slot comparator receives the first and second signals and generates a token work unique to the first and second signals. A data transfer circuit transfers a data word to or from the TDM bus responsive to the token word.
摘要翻译：用于控制对时分多路复用（TDM）总线的访问的装置包括具有多个存储寄存器的帧地址寄存器，用于存储指定用于通过所述TDM总线进行通信的多个帧地址。帧地址锁存器存储当前帧地址。耦合到帧地址寄存器和帧地址锁存器的帧比较器将指定的帧地址与当前帧地址进行比较，并产生指示包含与当前帧地址匹配的帧地址的存储寄存器的第一信号。时隙寄存器具有多个存储寄存器，用于存储指定用于通过所述TDM总线通信的时隙号。时隙发生器产生当前时隙号。耦合到时隙寄存器和时隙发生器的时隙比较器将指定的时隙号与当前时隙号进行比较，并产生指示包含与当前时隙号相匹配的时隙号的存储寄存器的第二信号。耦合到帧比较器和时隙比较器的令牌发生器接收第一和第二信号，并产生对第一和第二信号唯一的令牌工作。数据传输电路响应于令牌字将数据字传送到TDM总线或从TDM总线传送数据字。

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