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    • 5. 发明授权
    • Method and apparatus for channel equalization
    • 信道均衡的方法和装置
    • US07400677B2
    • 2008-07-15
    • US11220508
    • 2005-09-06
    • William Jones
    • William Jones
    • H03K5/159H04B1/10
    • H04L25/03343H04L25/03146
    • A method and apparatus is disclosed to overcome the effects of intersymbol interference during data transmission. Overcoming the effects of intersymbol interference makes possible higher data transmission rates for a given error rate. In one embodiment a receiver-transmitter pair is configured with a precode filter at the transmit side and a feed forward filter and a feedback filter at the receive side. Filter coefficients are calculated to reduce the undesirable effects of the channel, such as intersymbol interference. In one embodiment a training process occurs with the feedforward filter and a feedback filter, such that the first N coefficients of the feedback filter are set to zero. Thereafter, the coefficients of the feedforward filter are subject to spectral factorization and separated into minimum phase roots and maximum phase roots. The minimum phase roots comprise the precode filter coefficients and the maximum phase roots are established as feedforward filter coefficients.
    • 公开了一种克服数据传输期间符号间干扰的影响的方法和装置。 克服符号间干扰的影响使给定错误率的数据传输速率更高。 在一个实施例中,接收机 - 发射机对在发射侧配置有预编码滤波器,并且在接收侧配置有前馈滤波器和反馈滤波器。 计算滤波器系数以减少信道的不期望的影响,例如符号间干扰。 在一个实施例中,使用前馈滤波器和反馈滤波器进行训练处理,使得反馈滤波器的前N个系数被设置为零。 此后,前馈滤波器的系数进行频谱分解,并分为最小相位根和最大相位根。 最小相位根包括预编码滤波器系数,并且将最大相位根建立为前馈滤波器系数。
    • 8. 发明授权
    • Controller for delay locked loop circuits
    • 延迟锁定环路控制器
    • US07245540B2
    • 2007-07-17
    • US09874898
    • 2001-06-05
    • William JonesWen Li
    • William JonesWen Li
    • G11C7/00
    • G11C7/222G11C7/22
    • A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.
    • 提供了一种控制存储器件中的延迟锁定环(DLL)的方法。 DLL根据外部时钟信号产生内部时钟信号。 DLL不断响应存储器件的工作状态的变化,以保持外部和内部时钟同步。 该方法涉及防止DLL在诸如活动模式,读取模式或刷新模式的存储器件的操作模式期间响应于操作条件的变化,例如存储器件的电源电压的变化。
    • 9. 发明申请
    • Reverse bias hatchet reset spring
    • 反向偏置斧头复位弹簧
    • US20070131526A1
    • 2007-06-14
    • US11302758
    • 2005-12-14
    • William JonesPerry Gibson
    • William JonesPerry Gibson
    • H01H9/54
    • H01H3/3031
    • The present invention provides a spring offset device structured to extend between a circuit breaker frame and a trip mechanism. The offset device includes an offset member disposed on a trip device banana link, a spring anchor disposed on the frame assembly, and a spring extending between the offset member and the spring anchor. The spring anchor is spaced from the hatchet pin assembly and, preferably positioned so that the longitudinal axis of the spring remains on a single side of a hatchet pin assembly axis as the banana link moves between a closed position, an open position, and a reset position. The offset member and the spring anchor are structured so that, when the hatchet plate is in the closed position, the spring creates an opening force on the hatchet plate biasing the hatchet plate toward the open position, and when the hatchet plate is in the reset position, the spring creates a closing force on the hatchet plate biasing the hatchet plate toward the closed position.
    • 本发明提供一种构造成在断路器框架和跳闸机构之间延伸的弹簧偏移装置。 偏移装置包括设置在跳闸装置香蕉连杆上的偏移构件,设置在框架组件上的弹簧锚杆以及在偏置构件和弹簧锚固件之间延伸的弹簧。 弹簧锚杆与斧形销组件间隔开,优选地定位成使得当香蕉连杆在关闭位置,打开位置和复位之间移动时,弹簧的纵向轴线保持在斧形销组件轴线的单侧上 位置。 偏移构件和弹簧锚构造成使得当斧形板处于关闭位置时,弹簧在煞车板上产生朝向打开位置偏置斧形板的打开力,并且当斧形板处于复位状态时 位置上,弹簧在斧形板上产生一个关闭力,从而将斧形板偏向关闭位置。