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1. 发明申请

US20100157687A1 Method for Erasing a Flash Memory Cell or an Array of Such Cells Having Improved Erase Coupling Ratio 有权
标题翻译：擦除闪存单元或具有改善的擦除耦合比的这种单元阵列的方法
公开(公告)号：US20100157687A1
公开(公告)日：2010-06-24
申请号：US12645337
申请日：2009-12-22
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/06 , G11C16/16
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与之绝缘。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

2. 发明授权

US07974136B2 Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio 有权
标题翻译：擦除具有改善的擦除耦合比的这种单元的闪存单元或阵列的方法
公开(公告)号：US07974136B2
公开(公告)日：2011-07-05
申请号：US12645337
申请日：2009-12-22
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

3. 发明申请

US20090201744A1 Method For Erasing A Flash Memory Cell Or An Array Of Such Cells Having Improved Erase Coupling Ratio 有权
标题翻译：用于擦除闪存单元的方法或者具有改善的擦除耦合比的这样的单元阵列
公开(公告)号：US20090201744A1
公开(公告)日：2009-08-13
申请号：US12027654
申请日：2008-02-07
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/16
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

4. 发明授权

US07668013B2 Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio 有权
标题翻译：擦除具有改善的擦除耦合比的这种单元的闪存单元或阵列的方法
公开(公告)号：US07668013B2
公开(公告)日：2010-02-23
申请号：US12027654
申请日：2008-02-07
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

5. 发明授权

US06706592B2 Self aligned method of forming a semiconductor array of non-volatile memory cells 有权
标题翻译：形成非易失性存储单元的半导体阵列的自对准方法
公开(公告)号：US06706592B2
公开(公告)日：2004-03-16
申请号：US10146569
申请日：2002-05-14
申请人： Geeng-Chuan Michael Chern , Chien-Sheng Su
发明人： Geeng-Chuan Michael Chern , Chien-Sheng Su
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66545
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in trenches using a first layer of conducting material at the bottom of the trenches, and a second layer of conducting material along sidewalls of the trenches. An etch process is used to etch away portions of the first and second layers of the conductive material to form floating gate blocks of the conductive material having sloping portions that terminate in pointed edges formed along the trench sidewalls. The sharpness of the pointed edges are enhanced by the presence of the conductive material disposed along the trench sidewalls.
摘要翻译：一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，该半导体衬底在衬底上具有多个间隔开的隔离区域和在衬底上彼此基本上平行的有源区域。在沟槽底部使用第一层导电材料形成浮动栅极，并沿着沟槽的侧壁形成第二层导电材料。蚀刻工艺用于蚀刻掉导电材料的第一和第二层的部分，以形成具有沿着沟槽侧壁形成的尖锐边缘终止的倾斜部分的导电材料的浮动栅极块。通过沿着沟槽侧壁设置的导电材料的存在来增强尖锐边缘的锐度。

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