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1. 发明授权

US08949522B1 Performance of a stride-based prefetcher on an out-of-order processing unit (CPU) 有权
标题翻译：基于步幅的预取器在无序中央处理单元（CPU）上的性能
公开(公告)号：US08949522B1
公开(公告)日：2015-02-03
申请号：US13165736
申请日：2011-06-21
申请人： Gaurav Garg , David T. Hass
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： Systems, apparatusses, and methods are disclosed for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU). The present disclosure teaches a processor system that employs out-of-order stride prefetch units. The out-of-order stride prefetch units are utilized for issuing prefetches for out-of-order stride access patterns. In one or more embodiments, the out-of-order stride prefetch units examine the offsets between past virtual address (VA) accesses and the directions of the past VA accesses in order to generate an estimate of the underlying VA access stride of the executed program code (PC). In at least one embodiment, the out-of-order stride prefetch units use the estimate of the VA access stride in order to generate a prediction of future VA accesses. In some embodiments, after the out-of-order stride prefetch units have generated the prediction of future VA accesses, the out-of-order stride prefetch units prefetch the predicted future VA accesses.
摘要翻译：公开了用于改善无序中央处理单元（CPU）上的基于步长的预取器的性能的系统，装置和方法。本公开教导了采用无序步长预取单元的处理器系统。无序步幅预取单元用于发出无序步进访问模式的预取。在一个或多个实施例中，无序步长预取单元检查过去虚拟地址（VA）访问与过去VA访问的方向之间的偏移量，以便生成执行程序的基本VA访问步幅的估计代码（PC）。在至少一个实施例中，无序步长预取单元使用VA访问步幅的估计，以便生成将来VA访问的预测。在一些实施例中，在无序步幅预取单元已经产生未来VA访问的预测之后，无序步幅预取单元预取预测的未来VA访问。

2. 发明授权

US08671220B1 Network-on-chip system, method, and computer program product for transmitting messages utilizing a centralized on-chip shared memory switch 有权
标题翻译：片上系统，方法和计算机程序产品，用于使用集中式片上共享存储器交换机传输消息
公开(公告)号：US08671220B1
公开(公告)日：2014-03-11
申请号：US12325050
申请日：2008-11-28
申请人： Gaurav Garg , David T. Hass , Kaushik Kuila , Gaurav Singh
发明人： Gaurav Garg , David T. Hass , Kaushik Kuila , Gaurav Singh
IPC分类号： G06F15/167 , G06F15/173
CPC分类号： H04L47/10 , H04L49/103 , H04L49/109
摘要： A network-on-chip system, method, and computer program product are provided for transmitting messages utilizing a centralized on-chip shared memory switch. In operation, a message is sent from one of a plurality of agents connected on a messaging network. The message is received at a central shared memory switch, the central shared memory switch being in communication with each of the plurality of agents. Further, the message is transmitted from the central shared memory switch to a destination agent, the destination agent being one of the plurality of agents.
摘要翻译：提供了片上系统，方法和计算机程序产品，用于使用集中的片上共享存储器交换机来发送消息。在操作中，从连接在消息收发网络上的多个代理之一发送消息。消息在中央共享存储交换机处被接收，中央共享存储器交换机与多个代理中的每一个进行通信。此外，消息从中央共享存储交换机发送到目的地代理，目的地代理是多个代理之一。

3. 发明授权

US08566533B1 System, method, and computer program product for conditionally sending a request for data to a node based on a determination 有权
标题翻译：用于基于确定有条件地向节点发送数据请求的系统，方法和计算机程序产品
公开(公告)号：US08566533B1
公开(公告)日：2013-10-22
申请号：US12571233
申请日：2009-09-30
申请人： Gaurav Garg , David T. Hass
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0831
摘要： In operation, a first request for data is sent to a cache of a first node. Additionally, it is determined whether the first request can be satisfied within the first node, where the determining includes at least one of determining a type of the first request and determining a state of the data in the cache. Furthermore, a second request for the data is conditionally sent to a second node, based on the determination.
摘要翻译：在操作中，向数据的第一请求发送到第一节点的高速缓存。此外，确定在第一节点内是否可以满足第一请求，其中确定包括确定第一请求的类型并确定高速缓存中的数据的状态中的至少一个。此外，基于该确定，有条件地将第二请求数据发送到第二节点。

4. 发明授权

US08478811B2 Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip 失效
标题翻译：高级处理器采用基于信用的方案，用于在芯片上的多处理器系统中实现最佳数据包流
公开(公告)号：US08478811B2
公开(公告)日：2013-07-02
申请号：US12261808
申请日：2008-10-30
申请人： Gaurav Garg , David T. Hass
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F15/16 , G06F15/177 , G06F15/173 , H04L12/28
CPC分类号： H04L47/10 , G06F12/0813 , H04L47/39
摘要： A system, method, and computer program product are provided for optimal packet flow in a multi-processor system on a chip. In operation, a credit is allocated for each of a plurality of agents coupled to a messaging network, the allocating including reserving one or more entries in a receive queue of at least one of the plurality of agents. Additionally, a first credit is decremented in response to a first agent sending a message to a second agent, the plurality of agents including the first and second agents. Furthermore, one of the first credit or a second credit is incremented in response to a signal from the second agent.
摘要翻译：提供了一种系统，方法和计算机程序产品，用于在芯片上的多处理器系统中实现最佳分组流。在操作中，为耦合到消息收发网络的多个代理中的每个代理分配信贷，分配包括在多个代理中的至少一个代理的接收队列中保留一个或多个条目。另外，响应于第一代理向第二代理发送消息而减少第一信用，所述多个代理包括第一和第二代理。此外，响应于来自第二代理的信号，第一信用或第二抵免额中的一个被递增。

5. 发明授权

US09128771B1 System, method, and computer program product to distribute workload 有权
标题翻译：系统，方法和计算机程序产品分发工作量
公开(公告)号：US09128771B1
公开(公告)日：2015-09-08
申请号：US12633702
申请日：2009-12-08
申请人： Gaurav Garg , David T. Hass
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F9/46 , G06F15/16 , G06F9/50
CPC分类号： G06F9/5083 , G06F9/50 , G06F9/5005 , G06F9/5027 , G06F9/505 , G06F9/5088 , G06F9/546 , G06F2209/548
摘要： A system, method, and computer program product are provided for sending a message from a first queue to a second queue associated with a receiver agent in response to a request. In operation, a message is sent from a sender agent to a first queue. Additionally, a request is received at the first queue from a receiver agent. Furthermore, the message is sent from the first queue to a second queue associated with the receiver agent, in response to the request.
摘要翻译：提供了系统，方法和计算机程序产品，用于响应于请求将消息从第一队列发送到与接收方代理相关联的第二队列。在操作中，消息从发送方代理发送到第一个队列。另外，从接收方代理处接收到第一个队列的请求。此外，响应于该请求，将消息从第一队列发送到与接收方代理相关联的第二队列。

6. 发明授权

US08438337B1 System and method for conditionally sending a request for data to a home node 有权
标题翻译：用于有条件地向家庭节点发送数据请求的系统和方法
公开(公告)号：US08438337B1
公开(公告)日：2013-05-07
申请号：US12571230
申请日：2009-09-30
申请人： Gaurav Garg , David T. Hass
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0831 , G06F12/084 , G06F2212/1024 , G06F2212/2542
摘要： A system and method are provided for sharing data between a network including one or more network nodes. The network includes a number of individual network nodes and a home network node communicating with one another. The individual network nodes and the home network node include a plurality of processors and memory caches. The memory caches consist of private caches corresponding to individual processors, as well as shared caches which are shared among the plurality of processors of an individual node and accessible by the processors of the other network nodes. Each network node is capable of executing a hierarchy of data requests that originate in the private caches of an individual local network node. If no cache hits occur within the local network node, a conditional request is sent to the home network node to request data through the shared caches of the other network nodes.
摘要翻译：提供了一种用于在包括一个或多个网络节点的网络之间共享数据的系统和方法。网络包括多个单独的网络节点和彼此通信的家庭网络节点。各个网络节点和家庭网络节点包括多个处理器和存储器高速缓存。存储器高速缓存由对应于各个处理器的专用高速缓存组成，以及在单个节点的多个处理器之间共享且可由其他网络节点的处理器访问的共享高速缓存。每个网络节点能够执行源自个别本地网络节点的专用高速缓存中的数据请求的层次。如果在本地网络节点内没有发生高速缓存命中，则向家庭网络节点发送条件请求，以通过其他网络节点的共享缓存来请求数据。

7. 发明申请

US20090055496A1 ADVANCED PROCESSOR WITH CREDIT BASED SCHEME FOR OPTIMAL PACKET FLOW IN A MULTI-PROCESSOR SYSTEM ON A CHIP 失效
标题翻译：具有信用流程的先进处理器，用于芯片上的多处理器系统中的最佳分组流
公开(公告)号：US20090055496A1
公开(公告)日：2009-02-26
申请号：US12261808
申请日：2008-10-30
申请人： Gaurav Garg , David T. Hass
发明人： Gaurav Garg , David T. Hass
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F12/0813 , H04L47/39
摘要： A system, method, and computer program product are provided for optimal packet flow in a multi-processor system on a chip. In operation, a credit is allocated for each of a plurality of agents coupled to a messaging network, the allocating including reserving one or more entries in a receive queue of at least one of the plurality of agents. Additionally, a first credit is decremented in response to a first agent sending a message to a second agent, the plurality of agents including the first and second agents. Furthermore, one of the first credit or a second credit is incremented in response to a signal from the second agent.
摘要翻译：提供了一种系统，方法和计算机程序产品，用于在芯片上的多处理器系统中实现最佳分组流。在操作中，为耦合到消息收发网络的多个代理中的每个代理分配信贷，分配包括在多个代理中的至少一个代理的接收队列中保留一个或多个条目。另外，响应于第一代理向第二代理发送消息而减少第一信用，所述多个代理包括第一和第二代理。此外，响应于来自第二代理的信号，第一信用或第二抵免额中的一个被递增。

8. 发明授权

US09264380B2 Method and apparatus for implementing cache coherency of a processor 有权
标题翻译：用于实现处理器的高速缓存一致性的方法和装置
公开(公告)号：US09264380B2
公开(公告)日：2016-02-16
申请号：US13103041
申请日：2011-05-07
申请人： David T. Hass
发明人： David T. Hass
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/931 , G06F12/08
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/30
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

9. 发明申请

US20120066477A1 ADVANCED PROCESSOR WITH MECHANISM FOR PACKET DISTRIBUTION AT HIGH LINE RATE 失效
标题翻译：高分辨率处理器用于高速分组分配
公开(公告)号：US20120066477A1
公开(公告)日：2012-03-15
申请号：US13226384
申请日：2011-09-06
申请人： David T. Hass
发明人： David T. Hass
IPC分类号： G06F9/312
CPC分类号： H04L49/15 , G06F12/0813
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

10. 发明申请

US20120030445A1 ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM 有权
标题翻译：高级处理器翻译在多个系统中预览缓冲区管理
公开(公告)号：US20120030445A1
公开(公告)日：2012-02-02
申请号：US13195785
申请日：2011-08-01
申请人： David T. Hass , Basab Mukherjee
发明人： David T. Hass , Basab Mukherjee
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/0813 , H04L49/00
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

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