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1. 发明申请

US20120150473A1 CLOCK EDGE GROUPING FOR AT-SPEED TEST 失效
标题翻译：时钟边缘分组用于速度测试
公开(公告)号：US20120150473A1
公开(公告)日：2012-06-14
申请号：US12967885
申请日：2010-12-14
申请人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
IPC分类号： G06F19/00
CPC分类号： G01R31/31726 , G01R31/31922
摘要： A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.
摘要翻译：一种对时钟域进行分组的方法包括：通过向多个域组中的每个相应的一个组分配来自相同时钟源的那些测试时钟并具有唯一的时钟分频比，将多个测试时钟分离成多个域组; 按照大小顺序排列域组; 以及通过将多个域组中的相应一个组合添加到已经存在的测试时钟具有不同时钟源的多个部分中的第一部分来创建多个部分，并且创建新部分并将相应的一个当存在于多个域组中的相应一个域组中的相应一个域组中的测试时钟源自相应的相同时钟源并且具有不同的时钟分频比作为存在于所有先前创建的部分中的测试时钟时，多个域组到新部分。

2. 发明授权

US08538718B2 Clock edge grouping for at-speed test 失效
标题翻译：用于速度测试的时钟分组
公开(公告)号：US08538718B2
公开(公告)日：2013-09-17
申请号：US12967885
申请日：2010-12-14
申请人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
IPC分类号： G06F19/00
CPC分类号： G01R31/31726 , G01R31/31922
摘要： A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.
摘要翻译：一种对时钟域进行分组的方法包括：通过向多个域组中的每个相应的一个组分配来自相同时钟源的那些测试时钟并具有唯一的时钟分频比，将多个测试时钟分离成多个域组; 按照大小顺序排列域组; 以及通过将多个域组中的相应一个组合添加到已经存在的测试时钟具有不同时钟源的多个部分中的第一部分来创建多个部分，并且创建新部分并将相应的一个当存在于多个域组中的相应一个域组中的相应一个域组中的测试时钟源自相应的相同时钟源并且具有不同的时钟分频比作为存在于所有先前创建的部分中的测试时钟时，多个域组到新部分。

3. 发明申请

US20140040685A1 BUILT-IN-SELF-TEST (BIST) ORGANIZATIONAL FILE GENERATION 有权
标题翻译：内部自检（BIST）组织文件生成
公开(公告)号：US20140040685A1
公开(公告)日：2014-02-06
申请号：US13567127
申请日：2012-08-06
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
IPC分类号： G11C29/12
CPC分类号： G11C29/54 , G11C5/04 , G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译：本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。

4. 发明授权

US06868513B1 Automated multi-device test process and system 有权
标题翻译：自动多设备测试过程和系统
公开(公告)号：US06868513B1
公开(公告)日：2005-03-15
申请号：US09697364
申请日：2000-10-26
申请人： Sally S. Botala , Dale B. Grosch , Donald L. LaCroix , Douglas E. Sprague , Randolph P. Steel , Anthony K. Stevens
发明人： Sally S. Botala , Dale B. Grosch , Donald L. LaCroix , Douglas E. Sprague , Randolph P. Steel , Anthony K. Stevens
IPC分类号： G01R31/319 , G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14 , G06F11/00
CPC分类号： G01R31/31912
摘要： A method, system and software for automatically generating a test environment for testing a plurality of devices (DUTs) under test in a test system. The multiple devices are tested by mapping the plurality of DUTs into pins of the tester system to create pin data; inputting into a test program generator pattern data, generic test program rules and the pin data; generating a multi-DUT test program and multi-DUT pattern data; and controlling the test system through the test program. The resulting fail data is then logged to each DUT.
摘要翻译：一种用于自动生成用于在测试系统中测试被测试的多个设备（DUT）的测试环境的方法，系统和软件。通过将多个DUT映射到测试器系统的引脚来测试多个器件以产生引脚数据; 输入测试程序生成器模式数据，通用测试程序规则和引脚数据; 生成多DUT测试程序和多DUT模式数据; 并通过测试程序控制测试系统。然后将生成的故障数据记录到每个DUT。

5. 发明授权

US08239818B1 Data structure for describing MBIST architecture 有权
标题翻译：用于描述MBIST架构的数据结构
公开(公告)号：US08239818B1
公开(公告)日：2012-08-07
申请号：US13080055
申请日：2011-04-05
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Georgy S. Varghese
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Georgy S. Varghese
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14 , G11C29/12
摘要： A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.
摘要翻译：可以在芯片设计平台内使用的系统和相关数据结构来定义MBIST架构的结构。一种用于生成内置于自我测试（MBIST）设计文件中的内存的系统，包括用于处理组织文件（Org File）的工具，其中组织文件包括指定MBIST设计文件的结构并符合的代码行到工具定义的数据结构; 其中所述数据结构提供基础设施以描述：在设计级别的MBIST组件之间的关联; MBIST组件与分级测试端口在设计级别之间的关联; 以及在设计级别的MBIST组件之间的菊花链的串行顺序。

6. 发明授权

US08661399B1 Built-in-self-test (BIST) organizational file generation 有权
标题翻译：内置自检（BIST）组织文件生成
公开(公告)号：US08661399B1
公开(公告)日：2014-02-25
申请号：US13567127
申请日：2012-08-06
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
IPC分类号： G06F17/50
CPC分类号： G11C29/54 , G11C5/04 , G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译：本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。

7. 发明授权

US08595678B2 Validating interconnections between logic blocks in a circuit description 失效
标题翻译：验证电路描述中的逻辑块之间的互连
公开(公告)号：US08595678B2
公开(公告)日：2013-11-26
申请号：US13365370
申请日：2012-02-03
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译：公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接块和其他逻辑块。

8. 发明申请

US20130205268A1 VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION 失效
标题翻译：验证电路中逻辑块之间的互连
公开(公告)号：US20130205268A1
公开(公告)日：2013-08-08
申请号：US13365370
申请日：2012-02-03
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译：公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接块和其他逻辑块。

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