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    • 3. 发明申请
    • Doctor blade holder
    • 刮刀刀架
    • US20060225647A1
    • 2006-10-12
    • US11101349
    • 2005-04-07
    • Robert Reid
    • Robert Reid
    • B05C1/08
    • D21G3/005
    • A doctor blade holder has a top plate having a rear portion overlying a base structure and a front portion projecting forward from the base structure. Blade support members are carried by and cooperate with the front portion of the top plate to define forwardly open slots for receiving the doctor blade. A hinge is interposed between the rear portion of the doctor blade and the base structure. The hinge has a body portion defining a fulcrum about which the top plate pivots relative to the base structure, and has forwardly and rearwardly projecting integral flanges arranged respectively to underlie the top plate and overlie the base structure. The doctor blade holder has means for securing the forwardly projecting flanges to the top plate and for securing the rearwardly projecting flanges to the base structure.
    • 刮刀保持器具有顶板,该顶板具有覆盖基部结构的后部和从基部结构向前突出的前部。 刀片支撑构件由顶板的前部承载并配合,以限定用于接收刮刀的向前开口的槽。 铰链位于刮刀的后部与底座结构之间。 铰链具有限定支点的主体部分,顶板相对于基座结构枢转,并且具有分别布置在顶板下方并且覆盖在基部结构上的向前和向后突出的整体凸缘。 刮刀架具有用于将向前突出的凸缘固定到顶板并用于将向后突出的凸缘固定到基部结构的装置。
    • 4. 发明授权
    • Central processing apparatus for fault-tolerant computing
    • 用于容错计算的中央处理装置
    • US4453215A
    • 1984-06-05
    • US307525
    • 1981-10-01
    • Robert Reid
    • Robert Reid
    • G06F11/18G06F11/00G06F11/10G06F11/16G06F11/20G06F13/00G06F13/374
    • G06F11/1625G06F11/1641G06F11/2007G06F13/374G06F11/10G06F11/20
    • A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
    • 容错计算机系统在计算模块的单元之间提供在所有单元共同的总线结构上的信息传输,包括处理器单元和存储器单元以及一个或多个外围控制单元。 在总线结构和每个单元中,系统的信息处理部分可以具有重复的伙伴。 错误检测器检查总线结构和每个系统单元的操作,仅在无故障总线导体和无故障单元之间提供信息传输。 计算机系统可以通过仅使用无故障的导体和功能单元在基本上不发生故障的情况下以这种方式操作。 具有异常速度和简单性的仲裁电路提供计算模块的单元根据每个单元的优先级访问公共总线结构。 模块的单元检查输入和输出信号是否有错误,向其他模块单元发出检测到的错误信号,并禁止单元向总线结构发送潜在的错误信息。
    • 9. 发明授权
    • Digital data processing apparatus with pipelined memory cycles
    • 具有流水线存储循环的数字数据处理设备
    • US4866604A
    • 1989-09-12
    • US227471
    • 1988-08-01
    • Robert Reid
    • Robert Reid
    • G06F11/10G06F11/14G06F11/16G06F11/20G06F11/22G11C29/00
    • G06F11/165G06F11/1616G06F11/1641G06F11/167G06F11/22G11C29/74G06F11/10G06F11/1625G06F11/2015
    • A digital data processing apparatus utilizes a common bus structure for transferring information between functional units, including a processing unit, a peripheral control unit, and first and second memory units. Unit-to-unit information transfers are executed on the bus structure by pipelining signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle. A signalling element periodically generates a first signal indicative the necessity to refresh at least one dynamic memory element in the first memory unit. A memory refresh element normally responds to that first signal for executing a memory refresh cycle during at least one timing interval common to first and second pipelined transfer cycles. A signal is generated indicating the onset of the memory refresh cycle. A memory update element can respond to the update cycle for transferring information from the first memory unit to the second memory unit during a timing interval common to first and second pipelined transfer cycles. The update element generates a signal indicating of the onset of the update cycle.
    • 数字数据处理装置利用公共总线结构在包括处理单元,外围控制单元以及第一和第二存储器单元的功能单元之间传送信息。 通过流水线表示在多个定时间隔期间发生的传送周期的信号,在总线结构上执行单元到单元信息传输,并且包括多个相位,其中一个周期的相位不重叠并且在不同的相应定时中依次发生 传送周期的间隔。 信令元件周期性地产生指示刷新第一存储器单元中的至少一个动态存储器元件的必要性的第一信号。 存储器刷新元件通常在第一和第二流水线传输周期共同的至少一个定时间隔期间响应于该第一信号用于执行存储器刷新周期。 产生指示存储器刷新周期开始的信号。 存储器更新元件可以响应于在第一和第二流水线传输周期共同的定时间隔期间将信息从第一存储器单元传送到第二存储器单元的更新周期。 更新元件产生指示更新周期开始的信号。