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1. 发明授权

US08532200B1 System and method for side band communication in SERDES transmission/receive channels 有权
标题翻译： SERDES发送/接收通道中边带通信的系统和方法
公开(公告)号：US08532200B1
公开(公告)日：2013-09-10
申请号：US12868414
申请日：2010-08-25
申请人： Gang Wang , Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Gang Wang , Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： H04L7/033
CPC分类号： H04L25/4902 , H04L7/0008 , H04L27/24
摘要： A system includes a side band transmission module configured to combine side band data with a clock signal to generate a modified clock signal. The system also includes a serializer configured to provide a waveform corresponding to serialized input data. The modified clock signal adjusts at least one of a leading edge or a falling edge of N half cycles of the waveform based on the side band data to form a modified waveform. The serializer is configured to output the modified waveform. N is greater than or equal to 1.
摘要翻译：一种系统包括：边带传输模块，被配置为将边带数据与时钟信号组合以产生经修改的时钟信号。该系统还包括被配置为提供对应于串行输入数据的波形的串行器。经修改的时钟信号基于边带数据调整波形的N个半周期的前沿或下降沿中的至少一个以形成修改的波形。串行器被配置为输出修改的波形。 N大于或等于1。

2. 发明授权

US08774249B2 Spread-spectrum clock acquisition and tracking 失效
标题翻译：扩频时钟采集和跟踪
公开(公告)号：US08774249B2
公开(公告)日：2014-07-08
申请号：US12878634
申请日：2010-09-09
申请人： Gang Wang , Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Gang Wang , Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： H04B1/00
CPC分类号： H03L7/0807 , H03L7/0814 , H04L7/0025 , H04L7/033
摘要： Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal.
摘要翻译：具有相应方法和计算机可读介质的装置包括：相位检测器，被配置为产生表示恢复的扩频时钟信号和包括扩频时钟信号的串行数据流之间的相位差的误差信号; 以及相位选择器，被配置为基于来自扩展频谱时钟信号的当前扩频周期的误差信号和来自扩展频谱时钟的先前扩频周期的误差信号来提供恢复的扩频时钟信号信号。

3. 发明申请

US20110068836A1 SPREAD-SPECTRUM CLOCK ACQUISITION AND TRACKING 失效
标题翻译：传播时钟采集和跟踪
公开(公告)号：US20110068836A1
公开(公告)日：2011-03-24
申请号：US12878634
申请日：2010-09-09
申请人： Gang Wang , Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Gang Wang , Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： H03L7/00
CPC分类号： H03L7/0807 , H03L7/0814 , H04L7/0025 , H04L7/033
摘要： Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal.
摘要翻译：具有相应方法和计算机可读介质的装置包括：相位检测器，被配置为产生表示恢复的扩频时钟信号和包括扩频时钟信号的串行数据流之间的相位差的误差信号; 以及相位选择器，被配置为基于来自扩展频谱时钟信号的当前扩频周期的误差信号和来自扩展频谱时钟的先前扩频周期的误差信号来提供恢复的扩频时钟信号信号。

4. 发明授权

US09286202B1 Operation aware striping in parallel drives 有权
标题翻译：并行驱动器中的操作意识到条带化
公开(公告)号：US09286202B1
公开(公告)日：2016-03-15
申请号：US12403192
申请日：2009-03-12
申请人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： G06F12/02
CPC分类号： G06F11/1088 , G06F11/108 , G06F12/0246 , G06F2212/1016 , G06F2212/7208 , G06F2212/7211
摘要： Embodiments of the present invention provide a method comprising performing an operation on a first flash drive of a plurality of flash drives configured in a parallel flash drive architecture, wherein the operation occupies a flash controller corresponding to the first flash drive, sending a signal to a processor coupled with the parallel flash drive architecture to indicate that the flash controller is occupied, and writing data to two or more of the plurality of flash drives, other than the first flash drive, by striping the data amongst the two or more of the plurality of flash drives in response to the signal to the processor. Other embodiments may be described and/or claimed.
摘要翻译：本发明的实施例提供了一种方法，包括对并行闪存驱动架构中配置的多个闪存驱动器的第一闪存驱动器执行操作，其中该操作占据与第一闪存驱动器对应的闪存控制器，向处理器与并行闪存驱动器架构耦合以指示闪存控制器被占用，并且通过在多个闪存驱动器中的两个或更多个之间分割数据，将数据写入到除了第一闪存驱动器之外的多个闪存驱动器中的两个或更多个的闪存驱动器响应于处理器的信号。可以描述和/或要求保护其他实施例。

5. 发明申请

US20120327697A1 DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS 有权
标题翻译：分布式闪存存储管理系统
公开(公告)号：US20120327697A1
公开(公告)日：2012-12-27
申请号：US13603994
申请日：2012-09-05
申请人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： G11C5/06
CPC分类号： G06F12/0284 , G06F12/0692 , G06F2212/1041 , G06F2212/2022
摘要： A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory.
摘要翻译：闪速存储器存储系统可以包括闪存存储器管理器电路的几个模块，每个模块具有一些相关联的闪存。模块可以经由模块的闪速存储器存储管理器电路互连。通过将数据路由到模块的闪速存储器存储电路，系统可能能够将数据写入和/或从与各种模块相关联的闪存中读取数据。由于各种原因，使用这种读写操作，系统也可以重新定位数据。模块的闪存存储电路跟踪闪存中实际数据的位置。

6. 发明授权

US08296555B2 Preloader 有权
标题翻译：预加载器
公开(公告)号：US08296555B2
公开(公告)日：2012-10-23
申请号：US12559987
申请日：2009-09-15
申请人： Chee Hoe Chu , Wei Zhou , Ping Zheng , Po-Chien Chang
发明人： Chee Hoe Chu , Wei Zhou , Ping Zheng , Po-Chien Chang
IPC分类号： G06F9/24 , G06F9/00
CPC分类号： G06F9/4401 , G06F9/4406 , G06F9/445
摘要： This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer.
摘要翻译：本公开描述了用于减少用于引导计算机并将应用程序加载到计算机上的总时间的技术和/或装置。

7. 发明授权

US08996892B1 Power smart peripheral devices with external power supplies 有权
标题翻译：为外部电源供电智能外设
公开(公告)号：US08996892B1
公开(公告)日：2015-03-31
申请号：US13272745
申请日：2011-10-13
申请人： Chee Hoe Chu , Ping Zheng , Wei Zhou , Po-Chien Chang
发明人： Chee Hoe Chu , Ping Zheng , Wei Zhou , Po-Chien Chang
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/325 , Y02D50/20
摘要： A peripheral device includes a host interface, a power interface, a switch, a control module, and a regulator. The host interface transfers data between the peripheral device and a host. The power interface receives power from a power source. The power source is separate from the peripheral device and the host. The control module monitors the host interface and generates a control signal to transition the switch from a first state to a second state when the host interface does not receive an expected signal from the host. The regulator powers the control module and a circuit of the peripheral device based on the power received from the power source. The control module is separate from the circuit. The switch activates the control module, the regulator and the circuit when in the first state and deactivates the control module, the regulator and the circuit when in the second state.
摘要翻译：外围设备包括主机接口，电源接口，开关，控制模块和调节器。主机接口在外围设备和主机之间传输数据。电源接口从电源接收电源。电源与外围设备和主机分开。当主机接口没有从主机接收到期望的信号时，控制模块监视主机接口并产生控制信号以将交换机从第一状态转换到第二状态。调节器基于从电源接收的功率为控制模块和外围设备的电路供电。控制模块与电路分开。当处于第一状态时，该开关激活控制模块，调节器和电路，并且在处于第二状态时使控制模块，调节器和电路无效。

8. 发明申请

US20100254173A1 DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS 有权
标题翻译：分布式闪存存储管理系统
公开(公告)号：US20100254173A1
公开(公告)日：2010-10-07
申请号：US12754376
申请日：2010-04-05
申请人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： G11C5/06
CPC分类号： G06F12/0284 , G06F12/0692 , G06F2212/1041 , G06F2212/2022
摘要： A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory.
摘要翻译：闪速存储器存储系统可以包括闪存存储器管理器电路的几个模块，每个模块具有一些相关联的闪存。模块可以经由模块的闪速存储器存储管理器电路互连。通过将数据路由到模块的闪速存储器存储电路，系统可能能够将数据写入和/或从与各种模块相关联的闪速存储器读取数据。由于各种原因，使用这种读写操作，系统也可以重新定位数据。模块的闪存存储电路跟踪闪存中实际数据的位置。

9. 发明授权

US08886885B2 Systems and methods for operating a plurality of flash modules in a flash memory file system 有权
标题翻译：用于在闪速存储器文件系统中操作多个闪存模块的系统和方法
公开(公告)号：US08886885B2
公开(公告)日：2014-11-11
申请号：US12940377
申请日：2010-11-05
申请人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： G06F12/00 , G06F12/08 , G06F12/02
CPC分类号： G06F17/30218 , G06F12/0246 , G06F12/0813 , G06F12/0866
摘要： Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash controller in communication with the cache memory and the flash memory; wherein the flash controller of a first one of the flash modules is configured to operate the cache memories together as a global cache; wherein the flash controller of a second one of the flash modules is configured to operate a second one of the flash modules as a directory controller for the flash memories.
摘要翻译：具有相应方法和计算机可读介质的装置包括：多个闪存模块，其中每个闪存模块包括高速缓冲存储器; 闪存; 以及与高速缓冲存储器和闪速存储器通信的闪存控制器; 其中所述闪存模块中的第一闪存模块的所述闪存控制器被配置为将所述高速缓存存储器一起操作为全局高速缓存; 其中所述闪存模块中的第二闪存模块的所述闪存控制器被配置为将所述闪存模块中的第二闪存模块操作为所述闪存的目录控制器。

10. 发明授权

US08533387B1 Interface for solid-state memory 有权
标题翻译：固态存储器接口
公开(公告)号：US08533387B1
公开(公告)日：2013-09-10
申请号：US13431059
申请日：2012-03-27
申请人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
发明人： Wei Zhou , Chee Hoe Chu , Po-Chien Chang
IPC分类号： G06F12/00
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F2212/7201
摘要： Devices, systems, methods, and other embodiments associated with an interface for solid state memory are described. In one embodiment, an apparatus comprises an interface configured to receive and aggregate two or more different streams of disk drive commands into at least one aggregated command, where the interface is configured to translate the at least one aggregated command into at least one solid state memory command for accessing solid state memory. The interface is configured to transmit the at least one solid state memory command to a controller to be performed on the solid state memory.
摘要翻译：描述了与固态存储器的接口相关联的设备，系统，方法和其他实施例。在一个实施例中，一种装置包括被配置为将两个或多个不同的磁盘驱动器命令流接收并聚合成至少一个聚合命令的接口，其中接口被配置为将至少一个聚合命令转换成至少一个固态存储器用于访问固态存储器的命令。该接口被配置为将至少一个固态存储器命令发送到要在固态存储器上执行的控制器。

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