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    • 1. 发明申请
    • TECHNIQUES FOR REDUCED PIXEL SHADING
    • 减少像素着色的技术
    • US20150379761A1
    • 2015-12-31
    • US14319472
    • 2014-06-30
    • Gabor LiktorMarco SalviKarthik Vaidyanathan
    • Gabor LiktorMarco SalviKarthik Vaidyanathan
    • G06T15/20G06T15/80G06T11/00G06T17/10
    • G06T15/80G06T11/40G06T15/30
    • Various embodiments are generally directed to techniques for reducing processing demands of shading primitives in rendering a 2D screen image from a 3D model. A device includes a clipping component to clip a visible primitive of a 2D screen image derived from of a 3D model within a first area of the screen image covered by a shading pixel to form a polygon representing an intersection of the first area and the visible primitive; a first interpolation component to interpolate at least one attribute of vertices of the visible primitive to each vertex of the polygon; and a second interpolation component to interpolate color values of the vertices of the polygon to a point within a second area covered by a screen pixel of the screen image, the second area smaller than the first area and at least partly coinciding with the first area. Other embodiments are described and claimed.
    • 各种实施例通常涉及用于在从3D模型渲染2D屏幕图像时减少着色原语的处理需求的技术。 一种设备包括剪切部件,用于剪切由遮蔽像素覆盖的屏幕图像的第一区域内由3D模型导出的2D屏幕图像的可见原始图形,以形成表示第一区域和可见原始图像的交点的多边形 ; 将所述可见原语的顶点的至少一个属性的内插内插到所述多边形的每个顶点的第一插值部件; 以及第二内插分量,以将多边形的顶点的颜色值内插到由屏幕图像的屏幕像素覆盖的第二区域内的点,第二区域小于第一区域,并且至少部分地与第一区域重合。 描述和要求保护其他实施例。
    • 10. 发明申请
    • Programmable CORDIC Processor with Stage Re-Use
    • 可编程CORDIC处理器,具有舞台重复使用
    • US20100138632A1
    • 2010-06-03
    • US12327395
    • 2008-12-03
    • Phanimithra GangalakurtiKarthik VaidyanathanPartha Sarathy MuraliInduShekhar Ayyalasomayajula
    • Phanimithra GangalakurtiKarthik VaidyanathanPartha Sarathy MuraliInduShekhar Ayyalasomayajula
    • G06F15/76G06F7/00
    • G06F7/4818
    • A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.
    • CORDIC处理器具有多个级,每个级具有X输入,Y输入,符号输入,符号输出,X输出,Y输出,具有ROTATE或VECTOR值的模式控制输入,以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位,通过移位X个输入k次来产生输出的第二移位;当模式控制时,具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时,输入为ROTATE和Y输入的符号,形成第一移位输出和多路复用器输出的乘积的第一乘法器,形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出,从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。