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1. 发明申请

WO2010088257A3 SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION 审中-公开
公开(公告)号：WO2010088257A3
公开(公告)日：2010-08-05
申请号：PCT/US2010/022203
申请日：2010-01-27
申请人： GLOBAL FOUNDRIES INC. , SCHEIPER, Thilo , WEI, Andy , BEYER, Sven
发明人： SCHEIPER, Thilo , WEI, Andy , BEYER, Sven
IPC分类号： H01L21/28 , H01L21/266 , H01L21/8238 , H01L21/336 , H01L21/265 , H01L29/10 , H01L21/3213 , H01L29/51
摘要： In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material (212) in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions (204) and halo regions (205).

2. 发明申请

WO2011025804A1 WORK FUNCTION ADJUSTMENT IN HIGH-K GATES STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS 审中-公开
标题翻译：包括不同厚度的门电介质的高K栅格堆栈中的工作功能调整
公开(公告)号：WO2011025804A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046572
申请日：2010-08-25
申请人： GLOBALFOUNDRIES INC. , SCHEIPER, Thilo , WEI, Andy , TRENTZSCH, Martin
发明人： SCHEIPER, Thilo , WEI, Andy , TRENTZSCH, Martin
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823462 , H01L21/823857
摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species (254A) within the high-k dielectric material (253) with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species (254A), the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures (250A, 250B) may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors (260A, 260B) having a different thickness gate dielectric material may be avoided.
摘要翻译：在复杂的制造技术中，通过在高k电介质材料（253）内提供基本上相同的空间分布的功能调节物质（254A）的功函数，可以在早期制造阶段调整工作功能和晶体管元件的阈值电压在不同厚度的栅极电介质材料中。在加入功函数调整物质（254A）之后，可以通过选择性地形成额外的电介质层来调节栅介电材料的最终厚度，使得栅电极结构（250A，250B）的进一步构图可以用与常规制造技术的高度兼容性。因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管（260A，260B）的阈值电压的非常复杂的过程。

3. 发明申请

WO2010005526A1 DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR 审中-公开
标题翻译：在大块基板上形成的双栅极和三极晶体管和形成晶体管的方法
公开(公告)号：WO2010005526A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/003898
申请日：2009-06-30
申请人： ADVANCED MICRO DEVICES, INC. , WEI, Andy , MULFINGER, Robert , SCHEIPER, Thilo , KAMMLER, Thorsten
发明人： WEI, Andy , MULFINGER, Robert , SCHEIPER, Thilo , KAMMLER, Thorsten
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7851
摘要： Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas (211D, 211S), the fins (210) and isolation structures (208A) in a self- aligned manner within a bulk semiconductor material. After defining the basic fin structures (210), highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.
摘要翻译：可以基于增强的掩蔽状态形成诸如FinFETS和三栅极晶体管的三维晶体管结构，从而能够形成漏极和源极区域（211D，211S），鳍片（210）和隔离结构（208A））以体积半导体材料中的自对准方式。在定义了基本的翅片结构（210）之后，可以使用平面晶体管配置的高效制造技术，从而进一步提高三维晶体管配置的整体性能。

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