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1. 发明申请

US20070234009A1 Processor having a dedicated hash unit integrated within 失效
标题翻译：具有集成在其中的专用散列单元的处理器
公开(公告)号：US20070234009A1
公开(公告)日：2007-10-04
申请号：US11758892
申请日：2007-06-06
申请人： GILBERT WOLRICH , Matthew Adiletta , William Wheeler
发明人： GILBERT WOLRICH , Matthew Adiletta , William Wheeler
IPC分类号： G06F9/40
CPC分类号： G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还公开了基于执行上下文的切换和分支的指令。

2. 发明申请

US20060069882A1 Memory controller for processor having multiple programmable units 有权
标题翻译：具有多个可编程单元的处理器的存储器控制器
公开(公告)号：US20060069882A1
公开(公告)日：2006-03-30
申请号：US11232566
申请日：2005-09-21
申请人： William Wheeler , Bradley Burres , Matthew Adiletta , Gilbert Wolrich
发明人： William Wheeler , Bradley Burres , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F13/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。所述处理器还包括存储器控制系统，所述存储器控制系统具有第一存储器控制器，所述第一存储器控制器基于所述存储器引用是针对偶数存储体还是存储器的奇数存储器排序存储器引用;以及第二存储器控制器，内存引用是读取引用或写入引用。

3. 发明授权

US07620702B1 Providing real-time control data for a network processor 失效
标题翻译：为网络处理器提供实时控制数据
公开(公告)号：US07620702B1
公开(公告)日：2009-11-17
申请号：US09473571
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta , William Wheeler
IPC分类号： G06F15/177
CPC分类号： G06F15/17
摘要： A multiprocessor includes a module configured to collect status data, one or more processing engines, and a push engine. Part of the status data is collected from devices connected to a bus and indicates readiness of the devices to participate in data transfers over the bus. The processing engines schedule transfers of data packets between the processor and the devices. The push engine performs unsolicited transfers of a portion of the status data to the processing engines in response to the module collecting new status data.
摘要翻译：多处理器包括被配置为收集状态数据的模块，一个或多个处理引擎和推动引擎。状态数据的一部分从连接到总线的设备收集，并指示设备参与通过总线进行数据传输的准备状态。处理引擎在处理器和设备之间调度数据包的传输。响应于模块收集新的状态数据，推送引擎执行状态数据的一部分的未经请求的转移到处理引擎。

4. 发明授权

US07191309B1 Double shift instruction for micro engine used in multithreaded parallel processor architecture 有权
标题翻译：用于多线程并行处理器架构的微型引擎的双移位指令
公开(公告)号：US07191309B1
公开(公告)日：2007-03-13
申请号：US10070006
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew I. Adiletta , William Wheeler , Debra Bernstein , Donald Hooper
发明人： Gilbert Wolrich , Matthew I. Adiletta , William Wheeler , Debra Bernstein , Donald Hooper
IPC分类号： G06F9/315 , G06F9/32
CPC分类号： G06F9/30032 , G06F9/32
摘要： A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.
摘要翻译：一种操作处理器的方法包括连接第一字和第二字以产生中间结果，将中间结果移位指定的移位量并将移位的中间结果存储在第三个字中，以创建一个地址。

5. 发明授权

US06560667B1 Handling contiguous memory references in a multi-queue system 有权
标题翻译：处理多队列系统中的连续内存引用
公开(公告)号：US06560667B1
公开(公告)日：2003-05-06
申请号：US09473112
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F1318
CPC分类号： G06F13/1642
摘要： A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references, such that the arbiter services a same queue until the chaining bit is cleared.
摘要翻译：用于随机存取存储器的控制器具有控制逻辑，包括检测未完成存储器引用状态的仲裁器。控制器从存储器引用的多个队列中的一个队列中选择存储器引用。控制逻辑响应于存储器参考链接位，当设置允许连续存储器引用的特殊处理时，仲裁器服务相同的队列，直到链接位被清除。

6. 发明授权

US06728845B2 SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues 有权
标题翻译：用于并行处理器架构的SRAM控制器和用于使用读取/读取队列控制对RAM的访问的方法
公开(公告)号：US06728845B2
公开(公告)日：2004-04-27
申请号：US10208264
申请日：2002-07-30
申请人： Matthew J. Adiletta , William Wheeler , James Redfield , Daniel Cutter , Gilbert Wolrich
发明人： Matthew J. Adiletta , William Wheeler , James Redfield , Daniel Cutter , Gilbert Wolrich
IPC分类号： G06F1300
CPC分类号： G06F13/1642
摘要： A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.
摘要翻译：用于诸如静态RAM（SRAM）的随机存取存储器（RAM）的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。地址和命令队列包括存储读取存储器引用的读取队列。控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用排队。存储器控制器可以在并行处理系统中使用，并且还可以包括订单队列，锁定查找内容可寻址存储器（CAM）和读锁定失败队列。还描述了包括媒体访问控制器（MAC），网络处理器和SRAM控制器的系统以及用于控制RAM的方法。

7. 发明授权

US07681018B2 Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set 失效
标题翻译：提供大寄存器地址空间同时最大化多线程寄存器堆集的循环性能的方法和装置
公开(公告)号：US07681018B2
公开(公告)日：2010-03-16
申请号：US09760509
申请日：2001-01-12
申请人： Gilbert Wolrich , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F9/00
CPC分类号： G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还公开了基于执行上下文的切换和分支的指令。

8. 发明授权

US07111296B2 Thread signaling in multi-threaded processor 失效
标题翻译：线程信令在多线程处理器中
公开(公告)号：US07111296B2
公开(公告)日：2006-09-19
申请号：US10615280
申请日：2003-07-08
申请人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还描述了用于分组处理的程序线程通信方案。

9. 发明授权

US06625654B1 Thread signaling in multi-threaded network processor 失效
标题翻译：线程信令在多线程网络处理器中
公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用被读取引用或写入引用。还描述了用于分组处理的程序线程通信方案。

10. 发明授权

US06587906B2 Parallel multi-threaded processing 有权
标题翻译：并行多线程处理
公开(公告)号：US06587906B2
公开(公告)日：2003-07-01
申请号：US10339221
申请日：2003-01-09
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F1300
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译：描述了用于仲裁命令请求的并行多线程处理器系统和技术。该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。

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