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1. 发明申请

WO2011091309A1 STEREOSCOPIC VIDEO GRAPHICS OVERLAY 审中-公开
标题翻译：立体视频图形覆盖
公开(公告)号：WO2011091309A1
公开(公告)日：2011-07-28
申请号：PCT/US2011/022133
申请日：2011-01-21
申请人： GENERAL INSTRUMENT CORPORATION , LUTHRA, Ajay K. , KIM, Jae Hoon , RAMAMURTHY, Arjun , XU, Haifeng
发明人： LUTHRA, Ajay K. , KIM, Jae Hoon , RAMAMURTHY, Arjun , XU, Haifeng
IPC分类号： H04N13/00
CPC分类号： H04N13/261 , H04N13/10 , H04N13/139 , H04N13/156 , H04N13/183
摘要： Preparing a three dimensional (3D) video graphical overlay based on a two dimensional (2D) graphical image in a decoded stereoscopic video signal. This includes receiving the 2D graphical image and receiving 3D information associated with the 3D video graphical overlay. This also includes reproducing, using a processor, the 2D graphical image to form a first view graphical image and a second view graphical image in a graphics window. This also includes mapping the first and second view graphical images, using the 3D information, to frames in the 3D video to form a 3D video graphical overlay of a 3D video stream. This also includes blending the 3D video graphical overlay and the 3D video stream.
摘要翻译：基于解码立体视频信号中的二维（2D）图形图像准备三维（3D）视频图形叠加。这包括接收2D图形图像并接收与3D视频图形叠加相关联的3D信息。这还包括使用处理器再现2D图形图像以在图形窗口中形成第一视图图形图像和第二视图图形图像。这还包括使用3D信息将第一和第二视图图形图像映射到3D视频中的帧以形成3D视频流的3D视频图形叠加。这还包括混合3D视频图形叠加和3D视频流。

2. 发明公开

EP4314967A1 METHOD AND SYSTEM FOR DIGITAL PLANT SYSTEM MODEL CREATION AND SIMULATION AND STORAGE MEDIUM 审中-实审
公开(公告)号：EP4314967A1
公开(公告)日：2024-02-07
申请号：EP21943438.8
申请日：2021-05-31
申请人： Siemens Industry Software Inc. , Xu, Haifeng
发明人： CAO, Julu , SHI, Guirong , LI, Na , XU, Haifeng
IPC分类号： G05B19/418 , G06F30/20 , G06F9/455

3. 发明申请

WO2004056057A2 METHOD AND APPARATUS FOR PROVIDING A BUFFER ARCHITECTURE TO IMPROVE PRESENTATION QUALITY OF IMAGES 审中-公开
标题翻译：用于提供缓冲结构以提高图像呈现质量的方法和装置
公开(公告)号：WO2004056057A2
公开(公告)日：2004-07-01
申请号：PCT/US2003/039858
申请日：2003-12-15
申请人： GENERAL INSTRUMENT CORPORATION
发明人： XU, Haifeng , DIAMAND, Joe , LUTHRA, Ajay
IPC分类号： H04L12/56
CPC分类号： H04N21/23406 , H04N21/44004
摘要： [0043] A method and apparatus that employ a buffer management architecture to address various video quality issues that may occur at a client player are disclosed. The present invention employs one or more buffers to assist in the scheduling and delivery of rendered content to a player's output system. In one embodiment, the system employs a packet buffer, a frame buffer and an image buffer. One useful advantage of the present invention is the control of these buffers to meet a predefined QoS, thereby ensuring factors that may negatively affect the QoS in the real-time transport of high bandwidth content will be minimized.
摘要翻译：公开了一种采用缓冲器管理架构来解决客户端播放器可能发生的各种视频质量问题的方法和装置。本发明采用一个或多个缓冲器来帮助将播放的内容调度和传送给玩家的输出系统。在一个实施例中，系统采用分组缓冲器，帧缓冲器和图像缓冲器。本发明的一个有益的优点是控制这些缓冲器以满足预定义的QoS，从而确保可能对高带宽内容的实时传输中的QoS负面影响的因素最小化。

4. 发明申请

WO2008133620A1 HIGH POWER T/R SWITCH USING STACKED TRANSISTORS 审中-公开
标题翻译：使用堆叠晶体管的大功率T / R开关
公开(公告)号：WO2008133620A1
公开(公告)日：2008-11-06
申请号：PCT/US2007/010295
申请日：2007-04-26
申请人： UNIVERSITY OF FLORIDA , XU, Haifeng , O, Kenneth, K.
发明人： XU, Haifeng , O, Kenneth, K.
IPC分类号： H03K17/693 , H03K17/10 , H01L27/04
CPC分类号： H03K17/693 , H01L21/823892 , H03K17/102 , H03K2217/0018
摘要： A T/R switch circuit is provided. In a preferred embodiment, T/R switch circuit designs are provided that increase IP1 dB for T/R switches while maintaining IL less than ~1 dB. In an embodiment, the T/R switch circuit can incorporate a series transistor on the TX leg, 3-stack transistors on the RX leg, shunt 3-stack transistors on the TX node, and a shunt transistor on the RX node. The transistors can be formed using sub-design-rule (SDR) channel length to reduce insertion loss (IL) and can be located in isolated p-wells to provide an improved floating body. In addition, feed-forward metal capacitors can be included to improve the total voltage swing of stacked transistors. This circuit can be implemented in the UMC 130-nm mixed mode triple-well CMOS process.
摘要翻译：提供T / R开关电路。在优选实施例中，提供T / R开关电路设计，其在保持IL小于〜1dB的T / R开关的同时增加IP1dB。在一个实施例中，T / R开关电路可以并入TX脚上的串联晶体管，RX脚上的3堆叠晶体管，TX节点上的3堆叠晶体管，以及RX节点上的分流晶体管。可以使用子设计规则（SDR）通道长度来形成晶体管，以减少插入损耗（IL），并且可以位于隔离的p阱中以提供改进的浮体。此外，可以包括前馈金属电容器以改善堆叠晶体管的总电压摆幅。该电路可以在UMC 130nm混合模式三阱CMOS工艺中实现。

5. 发明申请

WO2014143122A1 DEVICES, SYSTEMS, AND METHODS FOR CONVERTING OR TRANSLATING DYNAMIC ADAPTIVE STREAMING OVER HTTP (DASH) TO HTTP LIVE STREAMING (HLS) 审中-公开
标题翻译：用于将HTTP（DASH）转换为HTTP活动流（HLS）的动态自适应流转换或转换的设备，系统和方法
公开(公告)号：WO2014143122A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/046909
申请日：2013-06-20
申请人： GENERAL INSTRUMENT CORPORATION
发明人： MOORTHY, Praveen N. , XU, Haifeng
IPC分类号： H04N21/262 , G06F17/30 , H04N21/435 , H04N21/4402 , H04N21/845 , H04N21/854
CPC分类号： H04L65/60 , G06F17/30017 , H04N21/26258 , H04N21/4358 , H04N21/44029 , H04N21/8456 , H04N21/85406
摘要： Provided herein are systems and methods that allow for converting or translating Dynamic Adaptive Streaming over HTTP (DASH) to HTTP Live Streaming (HLS) and vice versa.
摘要翻译：本文提供了允许通过HTTP（DASH）将动态自适应流转换或转换为HTTP Live Streaming（HLS）的系统和方法，反之亦然。

6. 发明申请

WO2006023199A1 HIGH TRANSCONDUCTANCE AND DRIVE CURRENT HIGH VOLTAGE MOS TRANSISTORS 审中-公开
标题翻译：高电压和驱动电流高压MOS晶体管
公开(公告)号：WO2006023199A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/026081
申请日：2005-07-21
申请人： UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC. , XU, Haifeng , O, Kenneth, Kyongyop
发明人： XU, Haifeng , O, Kenneth, Kyongyop
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/823425 , H01L21/823462 , H01L27/0705 , H01L29/7831
摘要： A composite MOS transistor (100) includes a first MOS sub-transistor (105) having a first gate dielectric thickness (106), and a second MOS sub-transistor (155) in series connection with the first MOS sub-transistor having a second gate dielectric thickness (107). The second gate dielectric thickness (107) is substantially thicker than the first gate dielectric thickness (106) preferably being at least 50% thicker. Composite MOS transistors generally provide a breakdown voltage (V ds ) approaching that of the second MOS sub-transistor (155) and a threshold voltage, transconductance and drive current all approaching that of the first MOS subtransistor (105), such as being within 20%, and preferably within 10%, of the reference parameter. A level shifting circuit includes first and at least a second drive transistor, wherein the drive transistors are composite MOS transistors.
摘要翻译：复合MOS晶体管（100）包括具有第一栅介质厚度（106）的第一MOS子晶体管（105）和与第二MOS子晶体管串联连接的第二MOS子晶体管（155），第二MOS子晶体管具有第二栅极电介质厚度栅介质厚度（107）。第二栅极电介质厚度（107）基本上比第一栅极电介质厚度（106）厚，优选地至少比厚度厚50％。复合MOS晶体管通常提供击穿电压（V

7. 发明公开

EP2526701A1 STEREOSCOPIC VIDEO GRAPHICS OVERLAY 无效转让
标题翻译：视频图形立体OVERLAY
公开(公告)号：EP2526701A1
公开(公告)日：2012-11-28
申请号：EP11703315.9
申请日：2011-01-21
申请人： General instrument Corporation
发明人： LUTHRA, Ajay K. , KIM, Jae Hoon , RAMAMURTHY, Arjun , XU, Haifeng
IPC分类号： H04N13/00
CPC分类号： H04N13/261 , H04N13/10 , H04N13/139 , H04N13/156 , H04N13/183
摘要： Preparing a three dimensional (3D) video graphical overlay based on a two dimensional (2D) graphical image in a decoded stereoscopic video signal. This includes receiving the 2D graphical image and receiving 3D information associated with the 3D video graphical overlay. This also includes reproducing, using a processor, the 2D graphical image to form a first view graphical image and a second view graphical image in a graphics window. This also includes mapping the first and second view graphical images, using the 3D information, to frames in the 3D video to form a 3D video graphical overlay of a 3D video stream. This also includes blending the 3D video graphical overlay and the 3D video stream.

8. 发明公开

EP1570609A2 METHOD AND APPARATUS FOR PROVIDING A BUFFER ARCHITECTURE TO IMPROVE PRESENTATION QUALITY OF IMAGES 审中-公开
标题翻译：方法和装置提供缓冲体结构的高画质化
公开(公告)号：EP1570609A2
公开(公告)日：2005-09-07
申请号：EP03790503.1
申请日：2003-12-15
申请人： GENERAL INSTRUMENT CORPORATION
发明人： XU, Haifeng , DIAMAND, Joe , LUTHRA, Ajay
IPC分类号： H04L12/56
CPC分类号： H04N21/23406 , H04N21/44004
摘要： A method and apparatus that employ a buffer management architecture to address various video quality issues that may occur at a client player are disclosed. The present invention employs one or more buffers to assist in the scheduling and delivery of rendered content to a player's output system. In one embodiment, the system employs a packet buffer, a frame buffer and an image buffer. One useful advantage of the present invention is the control of these buffers to meet a predefined QoS, thereby ensuring factors that may negatively affect the QoS in the real-time transport of high bandwidth content will be minimized.

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