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1. 发明专利

DE60106286D1 未知
公开(公告)号：DE60106286D1
公开(公告)日：2004-11-11
申请号：DE60106286
申请日：2001-08-31
申请人： GEN INSTRUMENT CORP
发明人： NEMIROFF S , LIU VINCENT , WU SIU-WAI
IPC分类号： H04N7/26 , H04N21/2343 , H04N21/236 , H04N21/2365 , H04N7/24
摘要： A system for providing an accurate time reference for multiple input and output digital video signals of a transcoder that is particularly suited for use with MPEG data. The multiple streams are synchronized with a single master system time clock at the transcoder. Timing data from the master clock is compared to timing data from packets that are input to the transcoder to determine an offset. In particular, timing data, such as a program clock reference (PCR) field, is recovered from packets of different channels that are input to the transcoder. For each channel, timing data is then provided for packets that are output from the transcoder based on the offset and timing data of the master clock at the respective output times. In particular, the adjusted timing data is determined as a sum of the offset and an associated hardware error, less a delay (PcrSysDly) associated with the transcoder, which includes a lookahead delay and a buffer delay. The associated hardware error represents an error of the master clock and/or a system time clock of an encoder that encoded the particular channel.

2. 发明专利

DE60106286T2 未知
公开(公告)号：DE60106286T2
公开(公告)日：2005-10-13
申请号：DE60106286
申请日：2001-08-31
申请人： GEN INSTRUMENT CORP
发明人： NEMIROFF S , LIU VINCENT , WU SIU-WAI
IPC分类号： H04N7/26 , H04N21/2343 , H04N21/236 , H04N21/2365 , H04N7/24
摘要： A system for providing an accurate time reference for multiple input and output digital video signals of a transcoder that is particularly suited for use with MPEG data. The multiple streams are synchronized with a single master system time clock at the transcoder. Timing data from the master clock is compared to timing data from packets that are input to the transcoder to determine an offset. In particular, timing data, such as a program clock reference (PCR) field, is recovered from packets of different channels that are input to the transcoder. For each channel, timing data is then provided for packets that are output from the transcoder based on the offset and timing data of the master clock at the respective output times. In particular, the adjusted timing data is determined as a sum of the offset and an associated hardware error, less a delay (PcrSysDly) associated with the transcoder, which includes a lookahead delay and a buffer delay. The associated hardware error represents an error of the master clock and/or a system time clock of an encoder that encoded the particular channel.

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